04.1 快取記憶體的 Verilog 設計#

// tag 陣列：64 行，每行 22 bit tag + 1 valid + 1 dirty = 24 bit
// 綜合器會推論成 64 x 24 的 BRAM（LUTRAM/BRAM 視大小而定）
reg [23:0] tag_array [0:63];

// data 陣列：64 行 x 4 words x 32 bit = 8192 bit，用 BRAM
reg [31:0] data_array [0:255];   // 攤平：index(6) * word(2) 位址空間

//=============================================================
// dcache_wt.v : 直接映射、write-through 快取，附 write buffer
// 組態: 64 行 x 4 words/block, 資料 32-bit
// 位址切分: tag = a[31:10], index = a[9:4], word = a[3:2]
//=============================================================
module dcache_wt #(
    parameter INDEX_BITS = 6,
    parameter WORDS_PER_BLOCK = 4,
    parameter WB_DEPTH = 8            // write buffer 深度
)(
    input  logic        clk,
    input  logic        rst,
    // CPU 側
    input  logic        cpu_req,
    input  logic        cpu_we,
    input  logic [31:0] cpu_addr,
    input  logic [31:0] cpu_wdata,
    output logic        cpu_ready,     // 本請求完成（一拍 ack）
    output logic [31:0] cpu_rdata,
    // 記憶體側（慢速主記憶體）
    output logic        mem_req,
    output logic        mem_we,
    output logic [31:0] mem_addr,
    output logic [31:0] mem_wdata,
    input  logic        mem_ready      // 記憶體完成（可多拍後拉高）
);
    localparam WORD_W   = $clog2(WORDS_PER_BLOCK);           // 2
    localparam INDEX_W  = INDEX_BITS;                        // 6
    localparam TAG_W    = 32 - WORD_W - 2 - INDEX_W;         // 22

    // ---- 資料與狀態陣列（推論 BRAM/LUTRAM）----
    logic [TAG_W-1:0]   tag_arr  [0:(1<<INDEX_BITS)-1];
    logic               valid_arr[0:(1<<INDEX_BITS)-1];
    logic [31:0]        data_arr [0:(1<<INDEX_BITS)*(1<<WORD_W)-1];

    // ---- 位址欄位拆解 ----
    wire [TAG_W-1:0]   req_tag   = cpu_addr[31:32-TAG_W];
    wire [INDEX_W-1:0] req_index = cpu_addr[WORD_W+2 +: INDEX_W];
    wire [WORD_W-1:0]  req_word  = cpu_addr[2 +: WORD_W];
    wire [INDEX_W+WORD_W-1:0] data_idx = {req_index, req_word};

    // ---- 命中判斷 ----
    wire hit = cpu_req & valid_arr[req_index] & (tag_arr[req_index] == req_tag);

    // ---- 讀取路徑：BRAM 同步讀，用輸出暫存器吸收 ----
    logic [31:0] rdata_r;
    always_ff @(posedge clk) rdata_r <= data_arr[data_idx];

    // ---- Write Buffer：FIFO 原語式的環狀佇列 ----
    // （許多 FPGA 工具也提供现成 FIFO IP；此處手寫以展示原理）
    logic [70:0] wb_mem [0:WB_DEPTH-1];   // {addr[31:0], data[31:0], we}
    logic [$clog2(WB_DEPTH):0] wb_wr, wb_rd;
    wire wb_empty = (wb_wr == wb_rd);
    wire wb_full  = (wb_wr[ $clog2(WB_DEPTH) ] != wb_rd[$clog2(WB_DEPTH)]) 
                    && (wb_wr[$clog2(WB_DEPTH)-1:0] == wb_rd[$clog2(WB_DEPTH)-1:0]);
    wire wb_flush_ready = ~wb_full;

    // CPU 寫入命中：同時寫 cache 與 write buffer
    always_ff @(posedge clk) begin
        if (cpu_req && cpu_we && hit && wb_flush_ready) begin
            data_arr[data_idx] <= cpu_wdata;
            wb_mem[wb_wr[$clog2(WB_DEPTH)-1:0]] <= {cpu_addr, cpu_wdata};
            wb_wr <= wb_wr + 1'b1;
        end
    end

    // Write buffer 背景 flush：不 empty 就向記憶體寫
    logic        fl_active;
    logic [31:0] fl_addr, fl_data;
    always_ff @(posedge clk) begin
        if (rst) begin
            fl_active <= 1'b0; wb_rd <= 0;
        end else if (!fl_active && !wb_empty) begin
            {fl_addr, fl_data} <= wb_mem[wb_rd[$clog2(WB_DEPTH)-1:0]];
            fl_active <= 1'b1;
            wb_rd     <= wb_rd + 1'b1;
        end else if (fl_active && mem_ready) begin
            fl_active <= 1'b0;
        end
    end

    // ---- 主控制器：讀 miss 處理 ----
    typedef enum logic [1:0] {IDLE, MISS_WAIT, MISS_FILL, MISS_ACK} state_t;
    state_t state;
    logic [31:0] miss_addr;
    logic [WORD_W-1:0] fill_cnt;

    // miss 時把請求鎖存，逐 word 讀回 block
    always_ff @(posedge clk) begin
        if (rst) begin
            state <= IDLE; valid_arr <= '{default:0};
            mem_req <= 1'b0; cpu_ready <= 1'b0;
        end else begin
            cpu_ready <= 1'b0;
            case (state)
              IDLE: if (cpu_req && !hit && !cpu_we) begin   // 讀 miss
                        miss_addr <= {cpu_addr[31:WORD_W+2], 2'b00};
                        tag_arr[req_index]   <= req_tag;
                        valid_arr[req_index] <= 1'b1;
                        // write-through：直接映射讀 miss 不需寫回舊行
                        state <= MISS_WAIT;
                    end
              MISS_WAIT: begin
                        mem_req   <= 1'b1;
                        mem_we    <= 1'b0;
                        mem_addr  <= {miss_addr[31:2] + fill_cnt, 2'b00};
                        state     <= MISS_FILL;
                    end
              MISS_FILL: if (mem_ready) begin
                        data_arr[{req_index, fill_cnt}] <= mem_wdata;
                        mem_req <= 1'b0;
                        if (fill_cnt == WORDS_PER_BLOCK-1) begin
                            fill_cnt <= 0;
                            state <= MISS_ACK;
                        end else begin
                            fill_cnt  <= fill_cnt + 1'b1;
                            state     <= MISS_WAIT;
                        end
                    end
              MISS_ACK: begin
                        cpu_ready  <= 1'b1;
                        cpu_rdata  <= data_arr[data_idx]; // 已填回
                        state      <= IDLE;
                    end
            endcase
        end
    end

    assign mem_wdata = fl_data;
    assign mem_we    = fl_active;
endmodule

logic [63:0] cnt_access, cnt_miss;
always_ff @(posedge clk) if (rst) begin
    cnt_access <= 0; cnt_miss <= 0;
end else begin
    if (cpu_req) begin
        cnt_access <= cnt_access + 1;
        if (cpu_req && !hit && !cpu_we) cnt_miss <= cnt_miss + 1; // 僅統計讀 miss
    end
end