04.3 DMA 與中斷控制器實作#

loop:
    lw   t0, 0(a0)        # 讀 1 word：hit 2 拍 / miss 18 拍
    sw   t0, 0(a1)        # 寫 1 word：write-through 打 write buffer
    addi a0, a0, 4
    addi a1, a1, 4
    addi a2, a2, -4
    bnez a2, loop

//=============================================================
// dma.v : 單通道 DMA，word 傳輸，讀一個 word 立刻寫一個 word
//=============================================================
module dma #(
    parameter BURST = 1          // 每次搶到匯流排連搬幾個 word
)(
    input  logic clk, rst,
    // slave 介面（CPU 寫命令）
    input  logic        sel, req, we,
    input  logic [7:0]  addr,
    input  logic [31:0] wdata,
    output logic [31:0] rdata,
    output logic        done,
    // master 介面（經仲裁器上匯流排）
    output logic        m_req,     // 請求使用匯流排
    input  logic        m_gnt,     // 仲裁器授權
    output logic        m_we,
    output logic [31:0] m_addr,
    output logic [31:0] m_wdata,
    input  logic [31:0] m_rdata,
    input  logic        m_done,    // slave 回應完成
    // 中斷
    output logic        irq
);
    logic [31:0] sa, da, len;
    logic        en_irq, busy;

    // ---- 暫存器讀寫 ----
    always_ff @(posedge clk) begin
        if (rst) begin
            sa <= 0; da <= 0; len <= 0; busy <= 0; en_irq <= 0;
        end else begin
            if (sel && req && we) case (addr[7:0])
                8'h00: sa    <= wdata;
                8'h04: da    <= wdata;
                8'h08: len   <= wdata;
                8'h0C: if (wdata[0]) begin
                           busy   <= 1'b1;
                           en_irq <= wdata[2];
                       end
            endcase
            if (busy && (len == 0)) busy <= 1'b0;   // 搬完停機
        end
    end

    always_comb begin
        rdata = 32'b0;
        case (addr[7:0])
            8'h00: rdata = sa;
            8'h04: rdata = da;
            8'h08: rdata = len;
            8'h0C: rdata = {28'b0, en_irq, ~busy, busy};
            default: rdata = 32'b0;
        endcase
    end
    assign done = sel && req;
    assign irq  = busy ? 1'b0 : (len == 0 && en_irq && (sa != 0)); // 完成脈衝，簡化

    // ---- 傳輸狀態機 ----
    // IDLE: 等 busy；REQ_RD: 搶匯流排發讀；RD_WAIT: 等 slave 給資料；
    // REQ_WR: 換成寫事務；WR_WAIT: 寫入完成；NEXT: 遞增位址與計數
    typedef enum logic [2:0] {IDLE, REQ_RD, RD_WAIT, REQ_WR, WR_WAIT, NEXT} st_t;
    st_t st;
    logic [31:0] data_hold, sa_r, da_r, len_r;

    always_ff @(posedge clk) begin
        if (rst) begin
            st <= IDLE; m_req <= 0; m_we <= 0;
        end else begin
            case (st)
              IDLE: if (busy && len_r != 0) begin
                        sa_r <= sa; da_r <= da; len_r <= len;
                        m_req <= 1'b1; m_we <= 1'b0; m_addr <= sa;
                        st <= REQ_RD;
                    end
              REQ_RD: if (m_gnt) st <= RD_WAIT;          // 已上匯流排
              RD_WAIT: if (m_done) begin
                        data_hold <= m_rdata;
                        m_we   <= 1'b1;
                        m_addr <= da_r;
                        m_wdata<= m_rdata;
                        st     <= REQ_WR;
                    end
              REQ_WR: if (m_gnt) st <= WR_WAIT;
              WR_WAIT: if (m_done) begin
                        m_req <= 1'b0;
                        st    <= NEXT;
                    end
              NEXT: begin
                        sa_r <= sa_r + 4;
                        da_r <= da_r + 4;
                        // 回寫進度到暫存器，CPU 可查
                        sa <= sa_r + 4; da <= da_r + 4;
                        if (len_r <= 4) len_r <= 0;
                        else len_r <= len_r - 4;
                        if (len_r > 4) begin
                            m_req <= 1'b1; m_we <= 1'b0;
                            m_addr <= sa_r + 4;
                            st <= REQ_RD;
                        end else st <= IDLE;
                    end
              default: st <= IDLE;
            endcase
        end
    end
endmodule

//=============================================================
// plic_lite.v : 8 個中斷源、單 hart、固定優先權（編號越大越高）
//=============================================================
module plic_lite (
    input  logic clk, rst,
    input  logic [7:0] src,        // 各中斷源的位準訊號
    // sBus slave 介面
    input  logic        sel, req, we,
    input  logic [7:0]  addr,
    input  logic [31:0] wdata,
    output logic [31:0] rdata,
    output logic        done,
    output logic        irq        // 送到 CPU 的中斷線
);
    logic [7:0] pending, enable;

    always_ff @(posedge clk) begin
        if (rst) pending <= 8'b0;
        else     pending <= (pending | src) & ~claim_clr;
    end

    // 固定優先權：編號 7 最高。用組合迴路找最高 pending & enable
    logic [7:0] cand;
    assign cand = pending & enable;
    logic [2:0] claim_id;
    logic       claim_valid;
    always_comb begin
        claim_id = 3'd0; claim_valid = 1'b0;
        for (int i = 7; i >= 0; i--) begin
            if (cand[i]) begin
                claim_id = 3'(i);
                claim_valid = 1'b1;
            end
        end
    end

    logic [7:0] claim_clr;
    always_ff @(posedge clk) claim_clr <= 8'b0;
    // 讀 claim (0x08) -> 清對應 pending；寫 complete (0x0C) -> 無動作（簡化）

    always_comb begin
        rdata = 32'b0;
        case (addr[7:0])
            8'h00: rdata = {24'b0, pending};
            8'h04: rdata = {24'b0, enable};
            8'h08: rdata = {28'b0, claim_valid, claim_id};   // CLAIM
            default: rdata = 32'b0;
        endcase
    end

    always_ff @(posedge clk) begin
        if (rst) enable <= 8'b0;
        else if (sel && req && we && addr[7:0] == 8'h04)
            enable <= wdata[7:0];
    end

    logic [7:0] claiming;
    always_ff @(posedge clk) begin
        if (rst) claiming <= 8'b0;
        else if (sel && req && !we && addr[7:0] == 8'h08 && claim_valid)
            claiming <= 8'b0;                     // 讀 claim 時清除（簡化：當拍）
    end
    assign claim_clr = claiming;                  // 正式版應按 claim_id 清單一個位元

    assign done = sel && req;
    assign irq  = |cand;                          // 有可服務中斷就拉高
endmodule