05.3 期末專題：微架構效能量測與改進#

/* core_portme.c —— 移植到自製 RISC-V SoC */
#include "coremark.h"
#include "uart.h"

#define NSECS_PER_SEC 100000000   /* 100MHz SoC */

/* 時間來源：CSR cycle 計數器（見下方） */
static unsigned long long begin_cycles, stop_cycles;

__attribute__((noinline))
void start_time(void) {
    unsigned hi, lo;
    asm volatile ("rdcycleh %0" : "=r"(hi));
    asm volatile ("rdcycle  %0" : "=r"(lo));
    begin_cycles = ((unsigned long long)hi << 32) | lo;
}

__attribute__((noinline))
void stop_time(void) {
    unsigned hi, lo;
    asm volatile ("rdcycleh %0" : "=r"(hi));
    asm volatile ("rdcycle  %0" : "=r"(lo));
    stop_cycles = ((unsigned long long)hi << 32) | lo;
}

CORETIMETYPE get_time(void) {
    return (CORETIMETYPE)(stop_cycles - begin_cycles);
}

void portable_fini(core_results *res) {
    double secs  = (double)res->time / NSECS_PER_SEC;
    double score = (double)res->iterations / secs;
    uart_puts("CoreMark 1.0 : ");
    print_u32((uint32_t)score);          /* 自行實作整數轉字串 */
    uart_puts(" / 100MHz = ");
    print_u32((uint32_t)(score / 100));
    uart_puts(" CoreMark/MHz\r\n");
}

// 在 CPU 內部（或 CSR 單元）加上：
reg [63:0] cycle_count;
always @(posedge clk) cycle_count <= cycle_count + 64'd1;
// Zicsr 讀取：0xC00 -> cycle, 0xC80 -> cycleh

riscv64-unknown-elf-gcc -march=rv32im -mabi=ilp32 -O2 \
    -ffunction-sections -fdata-sections -frename-registers \
    -DFLAGS_STR='"-O2 rv32im"' \
    core_main.c core_list_join.c core_matrix.c core_state.c \
    core_util.c core_portme.c uart_min.c crt0.S \
    -T link.ld -nostdlib -ffreestanding -o coremark.elf

// crc_cop.v —— CRC32 協同處理器（每拍處理 8 位元）
module crc_cop (
    input  wire        clk,
    input  wire        valid,     // CPU 發出自訂指令
    input  wire [2:0]  func,
    input  wire [31:0] rs1_data,  // 新資料 byte（低 8 位元）
    input  wire [31:0] rs2_data,  // 目前的 CRC 狀態
    output reg         ready,
    output reg  [31:0] result
);
    function [31:0] crc32_byte;
        input [31:0] crc;
        input [7:0]  data;
        reg [31:0] x;
        integer i;
        begin
            x = crc ^ {data, 24'b0};
            for (i = 0; i < 8; i = i + 1)
                x = x[31] ? (x << 1) ^ 32'h04C11DB7 : (x << 1);
            crc32_byte = x;
        end
    endfunction

    always @(posedge clk) begin
        ready  <= 1'b0;
        if (valid && func == 3'b000) begin
            ready  <= 1'b1;
            result <= crc32_byte(rs2_data, rs1_data[7:0]);
        end
    end
endmodule

wire is_custom = (instr[6:0] == 7'b0001011);   // custom-0
wire [2:0] cust_func = instr[14:12];
wire crc_sel = is_custom && (cust_func == 3'b000);
// 使流水線停等 1 拍，然後將 crc_result 寫回 rd

static inline uint32_t crc32_acc(uint32_t crc, uint8_t byte) {
    uint32_t out;
    asm volatile (".insn r 0x0B, 0, 0, %0, %1, %2"
                  : "=r"(out) : "r"(byte), "r"(crc));
    return out;
}

uint32_t crc32_buf(const uint8_t *p, int n) {
    uint32_t crc = 0xFFFFFFFF;
    for (int i = 0; i < n; i++)
        crc = crc32_acc(crc, p[i]);
    return ~crc;
}

Xr' = Xr + (Wr*Xi_r - Wi*Xi_i)
Xi' = Xi + (Wr*Xi_i + Wi*Xi_r)

// cmul_cop.v —— 16-bit 定點複數乘法：(ar+ai j)*(br+bi j)
module cmul_cop (
    input  wire        clk,
    input  wire        valid,
    input  wire [31:0] a,        // {ai[15:0], ar[15:0]}
    input  wire [31:0] b,        // {bi[15:0], br[15:0]}
    output reg         ready,
    output reg  [31:0] real_part // 僅回傳實部；虛部由第二條指令算
);
    wire signed [15:0] ar = a[15:0],  ai = a[31:16];
    wire signed [15:0] br = b[15:0],  bi = b[31:16];
    wire signed [31:0] pr = ar*br - ai*bi;
    always @(posedge clk) begin
        ready <= 1'b0;
        if (valid && func == 3'b001) begin
            ready <= 1'b1;
            real_part <= pr[29:14];   // Q15 定點，右移 14 回到 Q15
        end
    end
endmodule