3.1 四態值與 delta cycle#

// veryl/sim/src/sim.rs
pub struct Sim {
    ...
    pub nba: Vec<(usize, u32, u32, Val)>,   // 排程中的 NBA：(sig, bit lo, width, 值)
}

pub fn assign(&mut self, lv: &LValue, e: &Expr, nb: bool) {
    let Some((sig, lo, w)) = self.target(lv) else { return };
    let v = self.eval(e, w).resize(w);
    if nb { self.nba.push((sig, lo, w, v)); }   // <= : 只排程
    else  { self.write_bits(sig, lo, w, v); }   // =  : 立即寫
}

pub fn apply_nba(&mut self) {
    let q = std::mem::take(&mut self.nba);
    for (s, lo, w, v) in q { self.write_bits(s, lo, w, v); }
}

// veryl/sim/src/sim.rs  Design::settle
pub fn settle(&mut self) {
    for _ in 0..1000 {
        self.settle_comb();                      // (1) 組合邏輯收斂
        // (2) 邊緣偵測
        // (3) 觸發正反器
        // (4) 套用 NBA
    }
}

fn settle_comb(&mut self) {
    for it in 0..500 {
        // 比較整輪前後的狀態
        let before: Vec<(Bits, Bits)> = self.sim.sigs.iter().map(|s| (s.val.v, s.val.x)).collect();
        for p in &self.procs { if let Proc::Comb(b) = p { self.sim.exec(b, false); } }
        let same = self.sim.sigs.iter().zip(&before).all(|(s, b)| (s.val.v, s.val.x) == *b);
        if same { return; }
        if it == 499 { /* 警告：組合迴路沒有收斂 */ }
    }
}

// 對每個被 watch 的訊號（時脈與非同步重置）比較現在與上一次的值
let mut prev = vec![2u8; n];   // 2 = 「未知」
for &s in &self.watched {
    let b = bitv(&self.sim.sigs[s].val);
    let o = self.prev[s];
    if b != o {
        if b == 1 { pos[s] = true; any = true; }
        if b == 0 { neg[s] = true; any = true; }
    }
    self.prev[s] = b;
}
if !any { return; }   // 沒有任何邊緣 → 收斂完成

for p in &self.procs {
    if let Proc::Ff { clk, pos: edge_pos, rst, body } = p {
        let mut trig = if *edge_pos { pos[*clk] } else { neg[*clk] };
        if let Some((r, low, asynch)) = rst {
            if *asynch && ((*low && neg[*r]) || (!*low && pos[*r])) { trig = true; }
        }
        if trig { self.sim.exec(body, true); }     // NB: 非阻塞
    }
}
self.sim.apply_nba();

pub fn run(&mut self, max_time: u64) {
    let mut heap: BinaryHeap<Reverse<(u64, usize)>> = BinaryHeap::new();
    for (i, p) in self.procs.iter().enumerate() {
        if let Proc::ClockGen { half, .. } = p { heap.push(Reverse((*half, i))); }
    }
    self.sim.time = 0;
    self.settle();
    for (k) in 0..self.inits.len() { self.run_init(k); }
    self.settle();
    while !self.sim.finished {
        let Some(Reverse((t, _))) = heap.peek().copied() else { break };
        if t > max_time { break; }
        self.sim.time = t;
        while let Some(Reverse((t2, i))) = heap.peek().copied() {
            if t2 != t { break; }
            heap.pop();
            if let Proc::ClockGen { sig, half } = &self.procs[i] {
                let cur = self.sim.sigs[*sig].val.v.bit(0);
                self.sim.write_bits(*sig, 0, 1, Val::bit(!cur));   // .toggle
                heap.push(Reverse((t + *half, i)));
            }
        }
        self.settle();
        ...
    }
}

$timescale 1ns $end

// veryl/sim/src/value.rs
pub struct Val { pub w: u32, pub v: Bits, pub x: Bits, pub s: bool }

$assert(q != 8'hxx, "q must be reset before use");

/// 一個小小的二態閘級模擬器，在合成後的網表上執行，用來檢查綜合結果
/// （單一時脈域：step = 一個有效邊緣）
pub struct NetSim<'n> {
    nl: &'n Netlist,
    v: HashMap<u32, bool>,
    ...
}

/// 評價組合邏輯（單元依拓樸順序）；非同步重置可以改變正反器，所以重複直到穩定
pub fn settle(&mut self) {
    for _ in 0..4 {
        for c in &self.nl.cells {
            if c.is_ff() || c.typ == "SB_RAM40_4K" || c.typ == "SRAM" || c.typ == "DP16KD" || c.typ == "DIODE" { continue; }
            // 評價組合單元
        }
        // 檢查非同步重置是否改變了正反器；若是，再跑一輪
        if !changed { break; }
    }
}

"SB_LUT4" => {
    let idx = ["I0", "I1", "I2", "I3"].iter().enumerate()
        .fold(0, |a, (i, p)| a | ((g(p, self) as usize) << i));
    let init = &c.params.iter().find(|p| p.0 == "LUT_INIT").unwrap().1;
    init.as_bytes()[15 - idx] == b'1'
}

fn tree(init: u128, ins: &[Expr], k: usize, base: usize) -> Expr {
    if k == 0 { return Expr::Num(Val::new(1, (init >> base) & 1)); }
    let half = 1usize << (k - 1);
    let part = |b: usize| (init >> b) & ((1u128 << half) - 1);
    if part(base) == part(base + half) { return tree(init, ins, k - 1, base); }
    let (lo, hi) = (tree(init, ins, k - 1, base), tree(init, ins, k - 1, base + half));
    Expr::Tern(Box::new(ins[k - 1].clone()), Box::new(hi), Box::new(lo))
}

/// 輸入時脈 clk 的一個完整週期（上升，然後下降）：只有時脈接腳看到有效邊緣的
/// 正反器 / RAM 才擷取（多個時脈域、負沿正反器、經過緩衝器的時脈）
pub fn tick(&mut self, clk: &str) {
    let cells: Vec<Option<(Bit, bool)>> = self.nl.cells.iter().map(Self::clock_of).collect();
    self.set(clk, 0);
    for level in [1u128, 0] {
        let before: Vec<bool> = cells.iter().map(|c| c.map(|(p, _)| self.get_bit(p)).unwrap_or(false)).collect();
        self.set(clk, level);
        let sel: Vec<bool> = cells.iter().zip(&before).map(|(c, b)| match c {
            Some((p, rising)) => { let now = self.get_bit(*p); now != *b && now == *rising }
            None => false,
        }).collect();
        if sel.iter().any(|x| *x) { self.capture(&sel); }
    }
}

let pin = ["C", "CK", "RCLK", "CLK", "CLKB"].iter().find_map(|p| c.port(p))?;

/// （重置接腳, 高有效, 非同步, 值）
fn reset_of(c: &Cell) -> Option<(&'static str, bool, bool, bool)> {
    let t = c.typ.as_str();
    if t == "TRELLIS_FF" {
        // ECP5：LSR 經過 LSRMUX，值來自 REGSET，SRMODE 決定 ASYNC 或同步
        c.port("LSR")?;
        let p = |k: &str| c.params.iter().find(|x| x.0 == k).map(|x| x.1.as_str()).unwrap_or("");
        return Some(("LSR", p("LSRMUX") != "INV", p("SRMODE") == "ASYNC", p("REGSET") == "SET"));
    }
    // vlib 正反器：低有效非同步重置 / 設定
    match t {
        "DFFR" | "DFFNR" => return Some(("RN", false, true, false)),
        "DFFS" | "DFFNS" => return Some(("SN", false, true, true)),
        "DFF" | "DFFN" => return None,
        _ => {}
    }
    if let Some(k) = t.strip_prefix("SB_DFF") {
        // iCE40 的重置 / 設定都是高有效
        let k = k.trim_start_matches('N');
        let (sync, k) = if k.len() == 2 { (true, &k[1..]) } else { (false, k) };
        return match k { "R" => Some(("R", true, !sync, false)), "S" => Some(("S", true, !sync, true)), _ => None };
    }
    ...
}

/// 被選中的正反器與 RAM 取下一個狀態
fn capture(&mut self, sel: &[bool]) {

word = addr & 0xff
lane = (addr >> 8) & ((1 << rm) - 1)

for (w, d) in next { self.v.insert(w, d); }
for (w, d) in next_ram { self.v.insert(w, d); }
self.settle();

/// 網表上電：正反器為 0，記憶體為其初始內容
/// （通用網表的 $mem:NAME:init 網線、block RAM 的 INIT 參數）
pub fn new(nl: &'n Netlist) -> Self {
    ...
}

/// SB_RAM40_4K 的 256 個字，從它的 INIT_0..INIT_F（msb 優先，每個 16 個字）解出
fn ram40_words(c: &Cell) -> Vec<u16> {
    let mut ram = vec![0u16; 256];
    for (i, name) in crate::bram::INIT.iter().enumerate() {
        // ...
        for bit in 0..256 { if b[255 - bit] == b'1' { ram[i * 16 + bit / 16] |= 1 << (bit % 16); } }
    }
    ram
}

// veryl/sim/src/sim.rs  Vcd