4.1 網表 IR 與位元層級 Builder#

/// 一個位元：編譯期常數，或一條網線（net id >= 2，如 yosys JSON）
#[derive(Clone, Copy, PartialEq, Eq, Hash, Debug, PartialOrd, Ord)]
pub enum Bit {
    C0,
    C1,
    W(u32),
}

#[derive(Clone, Debug)]
pub struct Cell {
    pub typ: String,
    /// (接腳名稱, 位元)；輸出接腳是 "Y"（閘）、"O"（LUT）或 "Q"（正反器）
    pub conns: Vec<(&'static str, Bit)>,
    /// 單元參數（如同 LUT_INIT，msb 優先）
    pub params: Vec<(&'static str, String)>,
}

#[derive(Clone, Copy, PartialEq, Debug)]
pub enum Dir { In, Out }

#[derive(Clone)]
pub struct Port { pub name: String, pub dir: Dir, pub bits: Vec<Bit> }

#[derive(Clone)]
pub struct Netlist {
    pub name: String,
    pub ports: Vec<Port>,
    /// 具名網線（階層式名稱）
    pub nets: Vec<(String, Vec<Bit>)>,
    /// 組合單元依拓樸順序，接著是正反器
    pub cells: Vec<Cell>,
}

pub struct Builder {
    pub cells: Vec<Cell>,
    pub next_wire: u32,
    cache: HashMap<(&'static str, [Bit; 3]), Bit>,
    /// x <-> !x，因此雙重否定與 x & !x 會被折疊掉
    inv: HashMap<Bit, Bit>,
    /// 把多工器折疊進它選擇的兩個相同值之間
    /// （`s ? (t ? v : a) : a` = `(s & t) ? v : a`）
    pub fold_mux: bool,
    muxes: HashMap<Bit, [Bit; 3]>,
}

fn gate(&mut self, typ: &'static str, ins: &[(&'static str, Bit)]) -> Bit {
    let mut key = [Bit::C0; 3];
    for (k, (_, b)) in ins.iter().enumerate() { key[k] = *b; }
    if let Some(&y) = self.cache.get(&(typ, key)) { return y; }
    let y = self.wire();
    // ...
    self.cache.insert((typ, key), y);
    y
}

pub fn and(&mut self, a: Bit, b: Bit) -> Bit {
    match (a, b) {
        (Bit::C0, _) | (_, Bit::C0) => Bit::C0,
        (Bit::C1, x) | (x, Bit::C1) => x,
        _ if a == b => a,
        _ if self.is_inv(a, b) => Bit::C0,
        _ => {
            let (x, y) = (a.min(b), a.max(b));
            self.gate("$_AND_", &[("A", x), ("B", y)])
        }
    }
}

match (s, a, b) {
    (Bit::C0, _, _) => a,
    (Bit::C1, _, _) => b,
    (_, Bit::C0, Bit::C1) => s,        // 0 ? 1 : 0 == S
    (_, Bit::C1, Bit::C0) => self.not(s),
    (_, Bit::C0, _) => self.and(s, b),
    (_, _, Bit::C1) => self.or(s, a),
    // ...
}

always_ff (i_clk) {
    if cond1 { mem[i] = x; }
    if cond2 { mem[i] = y; }
}

/// x <-> !x，讓雙重否定與 x & !x 能折疊
inv: HashMap<Bit, Bit>,

pub fn not(&mut self, a: Bit) -> Bit {
    // 若 !a 已知，直接回傳
    // 否則建立新的 not 閘並記錄雙向關係
}

n => {
    let (l, r) = a.split_at(n / 2);
    let (x, y) = (self.reduce(l, unit, f), self.reduce(r, unit, f));
    f(self, x, y)
}

// p = x^y, g = x&y, pc = p&c, c' = g|pc

pub fn udivmod(&mut self, a: &[Bit], b: &[Bit]) -> (Vec<Bit>, Vec<Bit>)

pub fn shift(&mut self, a: &[Bit], amt: &[Bit], left: bool) -> Vec<Bit>

pub fn decode(&mut self, idx: &[Bit], k: usize) -> Vec<Bit>

pub struct Mem {
    pub name: String,
    pub depth: usize,
    pub width: usize,
    pub clk: Bit,
    pub we: Bit,
    pub waddr: Vec<Bit>,
    pub wdata: Vec<Bit>,
    pub reads: Vec<ReadPort>,
    /// 初始內容（init_words），若有
    pub init: Option<Vec<u128>>,
}

pub struct ReadPort {
    pub addr: Vec<Bit>,
    /// 讀取使能（C1 = 永遠啟用）
    pub en: Bit,
    /// 每個資料位元的讀取暫存器輸出（None = 該位元未使用）
    pub data: Vec<Option<Bit>>,
}

if width == 0 || store.len() % width != 0 { continue 'mem; }
let depth = store.len() / width;
let abits = bits_for(depth);
if depth != 1 << abits || wa.len() != abits { continue 'mem; }

let (ff, e) = if p == "D" && plain_ff(i) {
    (i, Bit::C1)                                        // 直接暫存器讀取
} else if p == "B" && c.typ == "$_MUX_" && !port_bits.contains(&c.out()) {
    // 使能：D = en ? rd : Q
    let uu = users.get(&c.out()).cloned().unwrap_or_default();
    if uu.len() != 1 || uu[0].1 != "D" || !plain_ff(uu[0].0)
        || c.port("A") != Some(nl.cells[uu[0].0].out()) { continue 'mem; }
    gone.push(i);
    (uu[0].0, c.port("S").unwrap())
} else { continue 'mem; };

// 記憶體大小之上的位址位元必須是 0（不容許環繞）
if ra.iter().skip(abits).any(|b| *b != Bit::C0) { continue 'mem; }

/// 緊湊的網線編號（2, 3, ...），依首次出現的順序
fn numbering(nl: &Netlist) -> HashMap<u32, u32> {
    let mut m = HashMap::new();
    let mut add = |b: Bit| if let Bit::W(w) = b { let n = m.len() as u32 + 2; m.entry(w).or_insert(n); };
    for p in &nl.ports { p.bits.iter().for_each(|b| add(*b)); }
    for c in &nl.cells { c.conns.iter().for_each(|(_, b)| add(*b)); }
    for (_, bits) in &nl.nets { bits.iter().for_each(|b| add(*b)); }
    m
}

{
  "creator": "rueda <version>",
  "modules": {
    "<name>": {
      "attributes": { "top": "00000000000000000000000000000001" },
      "ports": { "<port>": { "direction": "input|output", "bits": [ ... ] } },
      "cells": { "$veryl$0": { "type": "$_AND_", "connections": {...}, "parameters": {...} } },
      "netnames": { ... }
    }
  }
}

// 只含 0 / 1 的字串參數加上一個尾端空格（yosys 的 JSON 慣例），
// 否則它會被讀成位元向量
let sp = if crate::fpga::ecp5::is_string_param(&c.typ, k) && v.chars().all(|ch| ch == '0' || ch == '1') {
    " "
} else { "" };
format!("\"{}\": \"{}{}\"", k, v, sp)

let attrs: Vec<String> = c.params.iter().filter(|(k, _)| *k == crate::bram::SLOT)
    .map(|(_, v)| format!("\"veryl_mem\": \"{}\"", v)).collect();

let regs: HashSet<Bit> = nl.cells.iter()
    .filter(|c| c.is_ff() && c.typ.starts_with("$_"))
    .map(|c| c.out()).collect();

// $_DFF_P_ / $_DFF_PN0_ / $_SDFF_PP1_ ...
let f: Vec<char> = t.trim_start_matches("$_").trim_start_matches("S").trim_start_matches("DFF_").chars().collect();
let edge = if f[0] == 'P' { "posedge" } else { "negedge" };

// 索引接腳 "NAME[i]" 組成一個匯流排埠（缺少的輸入位元讀 0）
let bits: Vec<String> = (0..=top).rev().map(|k| match v.iter().find(|x| x.0 == k) {
    Some(x) => name(&x.1),
    None if is_out(p) => { dangling += 1; format!("nc{}_{}", i, dangling) }
    None => "1'b0".to_string(),
}).collect();
format!(".{}({{{}}})", p, bits.join(", "))

assign o_sum = a + b;