4.3 高階合成：從 task 到 FSM 與資料路徑#

.fx ──► parse（沿用 fluxa/sim 的 lexer/parser/AST）
     ──► fluxa/synth
          ① 展開   ：comptime 與 const 由既有直譯器求值；從 --top 靜態展開 spawn 樹；
                      泛型單體化；每個 chan 變成一個 FIFO
          ② 位寬推導：區間算術（int<lo..=hi>、fixed<I,F>）→ 每個運算式的靜態寬度
          ③ 降階   ：每個 task → 一個控制流程圖（迴圈、recv/send、if/match、@reg、carry）
          ④ 排程   ：先 FSM（每個通道操作是一個狀態邊界），再 pipeline(ii=n)
          ⑤ 產生網表：資料路徑、FSM、FIFO，寫進 eda::netlist 的位元層級 builder
     ──► eda::netlist::Netlist ──► 既有的 FPGA / ASIC / P&R 流程，完全不變

struct Recorder { spawns: Mutex<Vec<Spawn>> }
impl HwProvider for Recorder {
    fn start(&self, task: &str, args: &[(String, Value)]) -> Option<Result<Box<dyn HwTask>, String>> {
        self.spawns.lock().unwrap().push((task.to_string(), args.to_vec()));
        Some(Ok(Box::new(Idle)))       // 被錄到的任務什麼都不做
    }
}

let src_text = format!("task Broadcast(x: in chan<{}>{}) {{ for v in x {{ {}}} }}", elem, ps, sends);
let p2 = fluxa::load_many(&[("broadcast.fx".into(), src_text)])?;

// fluxa/synth/src/ty.rs
pub enum Ty {
    Int { lo: i128, hi: i128 },
    Bool,
    Fixed { i: u32, f: u32, round: Round, ovf: Ovf },
    Array(Box<Ty>, usize),
    Tuple(Vec<Ty>),
}

pub struct SVal {
    pub bits: Vec<Bit>,
    pub lo: i128, pub hi: i128,
    pub boolean: bool,
    pub frac: u32,
}

pub fn mul(g: &mut Builder, a: &SVal, b: &SVal) -> SVal {
    let p = [a.lo * b.lo, a.lo * b.hi, a.hi * b.lo, a.hi * b.hi];
    let (lo, hi) = (*p.iter().min().unwrap(), *p.iter().max().unwrap());
    let w = int_bits(lo, hi) as usize;
    let m = g.mul(&a.ext(w), &b.ext(w));
    ranged(m, lo, hi, a.frac + b.frac)     // 小數位數相加
}

// 對齊：位元數較少的小數的操作元左移
// T-FADD: fixed<I1,F1> + fixed<I2,F2> : fixed<max(I1,I2)+1, max(F1,F2)>
// T-FMUL: fixed<I1,F1> * fixed<I2,F2> : fixed<I1+I2, F1+F2>

// shl_sat 把結果夾在 ±2^120

// fluxa/synth/src/lower.rs
pub enum Term {
    Goto(B),
    Branch(Expr, B, B),
    Recv  { dst: String, ch: String, closed: Option<B>, next: B },
    Send  { ch: String, val: Expr, next: B },
    Close { ch: String, next: B },
    CloseOwned { ch: String, next: B },
    MemRead  { dst: String, mem: String, addr: Expr, next: B },
    MemWrite { mem: String, addr: Expr, val: Expr, next: B },
    Pipe { head: Option<(String,String)>, cond: Option<Expr>,
           recvs: Vec<(String,String)>, sends: Vec<(String,String)>, exit: B },
    Halt,
}
pub struct Bb { pub stmts: Vec<Stmt>, pub term: Term }
pub struct Cfg {
    pub blocks: Vec<Bb>,
    pub params: Vec<String>,
    pub temps: Vec<(String, Temp)>,
    pub mems: Vec<MemDecl>,
    pub warnings: Vec<String>,
}

// 每個綁定都取得唯一名字（x → x.3），作用域因此消失，變數變成暫存器

StmtKind::Let { pat: Ident(n), placement: Some("reg"), .. } => {
    regs.push(n.clone());
    stmts.push(s.clone());
    stmts.push(let_stmt(&format!("{}~p", n), path(n, line), line));
}

// acc += a.recv() * b.recv() 變成兩個接收狀態（依求值順序）
ExprKind::Method(r, n, _, a) if n == "recv" && a.is_empty() => {
    let dst = self.temp("recv", Temp::ChanElem(ch.clone()));
    let next = self.new_block();
    self.blocks[*cur].term = Term::Recv { dst: dst.clone(), ch, closed: None, next };
    *cur = next;
    Ok(Expr { kind: ExprKind::Path(vec![dst]), line })
}

// match_as_if：先把被比對值求值到一個變數
// else if 鏈共用一個結果變數，因此變成一個暫存器，而不是每層一個

Pipe { head: Option<(String,String)>, cond: Option<Expr>,
       recvs: Vec<(String,String)>, sends: Vec<(String,String)>, exit: B }

// 無型別的變數會不斷加寬直到放得下所有被指派的值
for round in 0.. {
    let mut t = Gen::new(prog); t.vars = vars.clone(); t.untyped = untyped.clone();
    temps(&mut t, cfg, &chans, &mems, &hw)?;
    for b in &cfg.blocks { t.stmts(&b.stmts)?; term_values(&mut t, &b.term, ...)?; }
    if !t.grew { vars = t.vars; untyped = t.untyped; break; }
    if round == 12 {
        return Err(format!("{}: variable(s) {} keep growing with every assignment: give them a type (or use `carry`)", ...));
    }
    vars = t.vars; untyped = t.untyped;
}

// state 是 bits_for(nstates) 位的暫存器，每個狀態解碼
g.decode(&state, s)

// 收集 (狀態條件, 值) 對，然後每一位元把「值與目前 Q 不同」的條件 OR 起來
for (c, v) in &ups {
    for i in 0..d.len() {
        if v[i] != qb[i] { d[i] = g.g.mux(*c, d[i], v[i]); }
    }
}

{channel}_data     資料
{channel}_close    end-of-stream
{channel}_valid    發送端：資料有效
{channel}_ready    接收端：可以接受

let fire = start && all sends ready;
// 每個 send 的致能排除其他 send 的 ready 訊號
let others: Vec<Bit> = readys.iter().enumerate().filter(|(j,_)| *j != k).map(|(_,r)| *r).collect();
let act = g.g.and(start, g.g.reduce_and(&others));

$mem:NAME:init
$mem:NAME:clk
$mem:NAME:we
$mem:NAME:wa
$mem:NAME:wd
$mem:NAME:ra0
$mem:NAME:rd0

// Gen 持有 fluxa::interp::Interp，用 block_on(self.it.eval(e)) 求值 comptime/const

fn fifo(b, rst, clk, depth, w, d, c, v, pop_ready) -> (Vec<Bit>, Bit, Bit, Bit) {
    let entries: Vec<Vec<Bit>> = (0..depth).map(|_| b.wires(w as u32 + 1)).collect();
    let (wr, rd, cnt) = ...;
    let push = b.and(v, push_ready);  let pop = b.and(pop_ready, pop_valid);
    let word = b.select(&entries, &rd);
    // push 端寫入 wr 位置的 entry（附上 close 旗標），pop 端讀出 rd 位置
    // 計數分別用 only_push / only_pop 更新
}

pub trait HwTask: Send {
    /// `offer`：每條輸入通道提供的 token；`room`：每條輸出通道還能不能收。
    fn cycle(&mut self, offer: &[Option<HwTok>], room: &[bool]) -> (Vec<bool>, Vec<Option<HwTok>>, bool);
    fn error(&self) -> Option<String> { None }
}

pub fn cycle(&mut self, offer: &[Option<Tok>], room: &[bool]) -> (Vec<bool>, Vec<Option<Tok>>) {
    // 對輸入 poke {c}_valid / {c}_close / {c}_data，對輸出讀 {c}_ready
    self.sim.settle();
    let taken = ... self.sim.get(&format!("{}_ready", n)) == 1 ...;
    let sent  = ... self.sim.get(&format!("{}_valid", n)) == 0 → None ...;
    let before: Vec<bool> = self.state.iter().map(|b| self.sim.bit(*b)).collect();
    self.sim.step();  self.sim.settle();
    self.changed = self.state.iter().zip(&before).any(|(b,v)| self.sim.bit(*b) != v);
    (taken, sent)
}