8.3 隨機測試、記分板與 cocotb 嵌入#

var r: $tb::random::<bit<12>>;

initial {
    r.seed(42);
    let x : bit<12> = r.get();            // 12-bit 隨機值
    let lo: bit<12> = r.get_range(0, 99); // [0, 99] 範圍內
}

var r_addr: $tb::random::<u32>;
var r_word: $tb::random::<u32>;

function gen_addr() -> u32 {
    var base: u32;
    loop {
        base = r_addr.get_range(0, 4095) & 32'hFFFF_FFFC; // 4-byte 對齊
        if base < 4096 {
            break;
        }
    }
    return base;
}

function gen_addr_biased() -> u32 {
    let sel: u32 = r_word.get_range(0, 9);
    case sel {
        0:      return 0;            // 邊界：最低位址
        1:      return 4092;         // 邊界：最高合法位址
        2:      return 4092 - 4 * r_word.get_range(0, 4); // 邊界附近
        default: return gen_addr();  // 一般均勻取樣
    }
}

#[test(test_fifo_random)]
module TestFifoRandom {
    inst clk: $tb::clock_gen #(period: 10);
    inst rst: $tb::reset_gen ( clk );
    inst u_fifo: SyncFifo #(
        WIDTH: 8,
        DEPTH : 16,
    ) (
        clk:    clk.clk,
        rst:    rst.rst,
        i_wr:   i_wr,
        i_data: i_data,
        i_rd:   i_rd,
        o_data: o_data,
        o_full: o_full,
        o_empty: o_empty,
    );

    var r_rand : $tb::random::<bit<8>>;
    var r_expc : $tb::queue::<u32, 64>;
    var r_cnt  : u32;

    var i_wr  : logic;
    var i_rd  : logic;
    var i_data: logic<8>;
    var o_data: logic<8>;
    var o_full: logic;
    var o_empty: logic;

    initial {
        r_rand.seed(1234);
        rst.assert();
        i_wr = 0;
        i_rd = 0;
        clk.next(5);

        // 隨機驅動 1000 個週期：寫入同時把期望值入隊 讀出時比對
        for i in 0..1000 {
            let do_wr: logic = if r_cnt < 16 && r_rand.get_range(0, 3) != 0 { 1 } else { 0 };
            let do_rd: logic = if r_cnt > 0  && r_rand.get_range(0, 3) != 0 { 1 } else { 0 };

            i_wr  = do_wr;
            i_rd  = do_rd;
            i_data = r_rand.get();
            if do_wr == 1 {
                r_expc.push_back(u32'(i_data));
            }

            clk.next(); // 交易生效

            if do_rd == 1 {
                let expect: u32 = r_expc.pop_front();
                $assert(o_data == logic<8>'(expect),
                    "cycle %d: pop got %h, expect %h", i, o_data, expect);
            }
        }
        $finish();
    }
}

function ref_alu(op: logic<2>, a: logic<8>, b: logic<8>) -> logic<9> {
    case op {
        Op::Add: return 9'(a) + 9'(b);
        Op::Sub: return 9'(a) - 9'(b);
        Op::And: return 9'(a & b);
        default: return 9'(a | b);
    }
}

// 隨機測試迴圈中：
for i in 0..500 {
    let rand_op: logic<2> = r_rand.get();
    let rand_a : logic<8> = r_rand.get();
    let rand_b : logic<8> = r_rand.get();
    op = rand_op; a = rand_a; b = rand_b;
    clk.next();
    let expected: logic<9> = ref_alu(rand_op, rand_a, rand_b);
    $assert({carry, y} == expected,
        "iter %d: dut=%h ref=%h op=%d a=%h b=%h", i, {carry, y}, expected, rand_op, rand_a, rand_b);
}

# cocotb 的典型樣貌
@cocotb.test()
async def test_fifo(dut):
    await RisingEdge(dut.i_clk)
    dut.i_wr.value = 1
    dut.i_data.value = 0xAB
    await RisingEdge(dut.i_clk)
    assert dut.o_data.value == 0xAB

#[test(test_fifo_cocotb, TestFifoTarget)]
module TestFifoTarget {
    inst clk: $tb::clock_gen #(period: 10);
    // DUT 實例化由 Veryl 負責 Python 端以層級路徑存取訊號
}

embed (cocotb) py{{{
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer

@cocotb.test()
async def test_fifo_cocotb(dut):
    cocotb.start_soon(Clock(dut.i_clk, 10, units="ns").start())

    dut.i_rst.value = 1
    await RisingEdge(dut.i_clk)
    dut.i_rst.value = 0
    await RisingEdge(dut.i_clk)

    # 寫入
    dut.i_wr.value = 1
    dut.i_data.value = 0xAB
    await RisingEdge(dut.i_clk)
    dut.i_wr.value = 0

    # 讀出並比對
    dut.i_rd.value = 1
    await RisingEdge(dut.i_clk)
    dut.i_rd.value = 0
    assert dut.o_data.value == 0xAB, (
        f"fifo pop = {dut.o_data.value}, expected 0xAB"
    )
}}};

#[test(test1)]
embed (inline) sv{{{
module test1;
    // 這裡是完整的 SystemVerilog testbench
    // 可以是既有 UVM 環境的進入點
    initial begin
        $display("hello from SV testbench");
        // run_uvm_test("my_uvm_test");
        $finish;
    end
endmodule
}}};

// 1. 命中計數器（模組級別的情境編號）
var r_hits: logic<32> [8];

// 2. 模擬中隨交易更新
always_ff {
    case i_txn_kind {
        Kind::Write:     r_hits[0] += 1;
        Kind::Read:      r_hits[1] += 1;
        Kind::WrWhileFull:  r_hits[2] += 1;
        Kind::RdWhileEmpty: r_hits[3] += 1;
        default:         {},
    }
}

// 3. final 報告
final {
    for i in 0..4 {
        if r_hits[i] == 0 {
            f.write("COVERAGE MISS: scenario %d\n", i);
        } else {
            f.write("scenario %d: hit %d times\n", i, r_hits[i]);
        }
    }
}