2.1 Delta 週期與 NBA 排程#

// veryl-sim/src/sim.rs
pub struct Sim {
    ...
    pub changed: bool,
    pub nba: Vec<(usize, u32, u32, Val)>,   // 排程中的 NBA：(sig, bit lo, width, 值)
    ...
}

pub fn assign(&mut self, lv: &LValue, e: &Expr, nb: bool) {
    let Some((sig, lo, w)) = self.target(lv) else { return };
    let v = self.eval(e, w).resize(w);
    if nb { self.nba.push((sig, lo, w, v)); }   // <= : 只排程
    else  { self.write_bits(sig, lo, w, v); }   // =  : 立即寫
}

pub fn apply_nba(&mut self) {
    let q = std::mem::take(&mut self.nba);
    for (s, lo, w, v) in q { self.write_bits(s, lo, w, v); }
}

// veryl-sim/src/sim.rs  Design::settle
pub fn settle(&mut self) {
    for _ in 0..1000 {
        self.settle_comb();                      // (1) 組合邏輯收斂
        let n = self.sim.sigs.len();
        let (mut pos, mut neg, mut any) = (vec![false; n], vec![false; n], vec![]);
        // ... 對 watched 訊號比較前後值，偵測 posedge / negedge ...
        if !any { return; }                      // (2) 沒有任何事件 → 穩定
        // (3) initial 區塊的 clk.next(n) 計數
        for st in &mut self.inits {
            if let Some((c, ref mut k)) = st.wait {
                if pos[c] && *k > 0 { *k -= 1; }
            }
        }
        // (4) 觸發的 flip-flop：執行 body（NBA）
        for p in &self.procs {
            if let Proc::Ff { clk, pos: edge_pos, rst, body } = p {
                let mut trig = if *edge_pos { pos[*clk] } else { neg[*clk] };
                if let Some((r, low, asynch)) = rst {
                    if *asynch && ((*low && neg[*r]) || (!*low && pos[*r])) { trig = true; }
                }
                if trig { self.sim.exec(body, true); }
            }
        }
        self.sim.apply_nba();                    // (5) NBA 區域
    }
    self.sim.say(&format!("warning: event loop did not settle ..."), true);
}

// veryl-sim/src/sim.rs
fn settle_comb(&mut self) {
    for it in 0..500 {
        // 比較整輪 pass 前後的狀態：一個區塊寫同一訊號兩次
        // (`x = 0; x += 1;`) 是合法的，不能只看單一 write
        let before: Vec<(Bits, Bits)> = self.sim.sigs.iter().map(|s| (s.val.v, s.val.x)).collect();
        for p in &self.procs {
            if let Proc::Comb(b) = p { self.sim.exec(b, false); }
        }
        let same = self.sim.sigs.iter().zip(&before).all(|(s, b)| (s.val.v, s.val.x) == *b);
        if same { return; }
        if it == 499 { /* warning: combinational loop did not settle */ }
    }
}

// veryl-sim/src/sim.rs  Design::run
pub fn run(&mut self, max_time: u64) {
    let mut heap: BinaryHeap<Reverse<(u64, usize)>> = BinaryHeap::new();
    for (i, p) in self.procs.iter().enumerate() {
        if let Proc::ClockGen { half, .. } = p { heap.push(Reverse((*half, i))); }
    }
    self.sim.time = 0;
    self.settle();                       // t=0 的初始化與組合收斂
    for k in 0..self.inits.len() { self.run_init(k); }
    self.settle();
    while self.resume_ready() && !self.sim.finished { self.settle(); }
    self.dump();
    while !self.sim.finished {
        let Some(Reverse((t, _))) = heap.peek().copied() else { break };
        if t > max_time { /* 達到 --max-time */ break; }
        self.sim.time = t;
        // 同一時間點的所有時脈緣一起處理
        while let Some(Reverse((t2, i))) = heap.peek().copied() {
            if t2 != t { break; }
            heap.pop();
            if let Proc::ClockGen { sig, half } = &self.procs[i] {
                let cur = self.sim.sigs[*sig].val.v.bit(0);
                self.sim.write_bits(*sig, 0, 1, Val::bit(!cur));
                heap.push(Reverse((t + *half, i)));   // 半週期後再翻轉
            }
        }
        self.settle();                   // 這個 posedge 引發的全部 delta 活动
        while self.resume_ready() && !self.sim.finished { self.settle(); }
        self.dump();
    }
    ...
}

// veryl-sim/src/sim.rs  Design::run_init (節錄)
Op::Exec(s) => {
    self.sim.exec(std::slice::from_ref(&s), false);
    // 每個敘述後都 settle：同一 initial 中後面的讀取
    // 才能看到組合邏輯的最新值（delta cycles）
    self.settle();
}
Op::Wait(clk, n) => {
    let n = self.sim.eval(&n, 0).v.sat();
    if n > 0 { self.inits[k].wait = Some((clk, n)); return; }
}

// veryl-sim/src/elab.rs  always_ff()
self.watched.push(clk);
if let Some((r, _, true)) = rinfo { self.watched.push(r); }   // 只追非同步 reset