2.3 精細化與層次展開#

// veryl-sim/src/sim.rs
pub struct Signal {
    pub name: String,          // 展開後的完整名（"u0.core.pc"）
    pub w: u32,
    pub signed: bool,
    pub kind: Kind,            // Normal / Clock / Reset
    pub val: Val,
    pub arr: Option<u32>,      // 陣列：本訊號是第 0 元素，後面 n 個連續
    pub fields: Vec<(String, u32, u32)>,   // struct 欄位 (名, 位元偏移, 寬)
}

// veryl-sim/src/elab.rs
#[derive(Default, Clone)]
pub struct Scope {
    pub prefix: String,                    // 層次前綴，如 "u0.core"
    pub sigs: HashMap<String, usize>,      // 區域名 -> 訊號索引
    pub params: HashMap<String, Val>,      // 參數/常數
    pub ports: Vec<(String, Dir, usize)>,  // 埠（供上層接線）
    pub imports: HashMap<String, String>,  // import Pkg::* 的別名
}

// veryl-sim/src/elab.rs  declare()（節錄）
let full = if sc.prefix.is_empty() { name.to_string() } else { format!("{}.{}", sc.prefix, name) };
let id = self.sim.sigs.len();
self.sim.sigs.push(Signal { name: full, ..., val, ... });
sc.sigs.insert(name.to_string(), id);

// veryl-sim/src/elab.rs
pub fn elab_module(&mut self, m: &'a ModuleDeclaration, prefix: &str, ov: &HashMap<String, Val>) -> R<Scope> {
    let mut sc = Scope { prefix: prefix.to_string(), ..Default::default() };
    if let Some(wp) = &m.module_declaration_opt1 { self.params(&mut sc, &wp.with_parameter, ov)?; }
    // 埠（含 modport 拆解，見 2.3.6）
    ...
    // pass 1: 宣告（其他項目可能引用）
    for it in &items { self.pass1(&mut sc, it)?; }
    // pass 2: 行為
    let cx = Cx { reset: None };
    for it in &items { self.pass2(&mut sc, it, &cx)?; }
    Ok(sc)
}

// veryl-sim/src/elab.rs  params()（節錄）
let mut val = if let Some(v) = ov.get(&name) { *v }                 // 實例的 #(...) 覆寫
              else if let Some(o) = &it.with_parameter_item_opt {
                  let t = toks(|c| c.expression(&o.expression));
                  self.const_in(&sc, &t)?                            // 預設值（可引用前面的參數）
              } else { return Err(format!("parameter '{}' has no value", name)) };
if let Some(ty) = ty { val = val.resize(ty.w).signed(ty.signed); }
sc.params.insert(name, val);

// veryl-sim/src/elab.rs（節錄）
let prefix = if sc.prefix.is_empty() { iname.clone() } else { format!("{}.{}", sc.prefix, iname) };
let csc = match (&gate, child) {
    (Some(g), _) => self.elab_gates(g, &prefix)?,       // 閘級網表（2.7 節）
    (None, Some(m)) => self.elab_module(m, &prefix, &ov)?,   // 遞迴展開 RTL
    _ => unreachable!(),
};
for (pname, dir, psig) in &csc.ports {
    let (base, member) = match pname.split_once('.') { Some((b, m)) => (b.to_string(), Some(m.to_string())), None => (pname.clone(), None) };
    let Some((_, expr)) = conns.iter().find(|(n, _)| *n == base) else { continue };
    ...
    let e = self.parse_in(sc, &t)?;
    match dir {
        Dir::In  => self.procs.push(Proc::Comb(vec![Stmt::Assign(LValue { sig: *psig, ... }, e)])),
        Dir::Out => self.procs.push(Proc::Comb(vec![Stmt::Assign(lv, Expr::Sig(*psig))])),
        Dir::Inout => return Err("inout ports are not supported".into()),
    }
}

// veryl-sim/src/elab.rs  instantiate() 的介面分支（節錄）
if let Some(&d) = self.ifaces.get(&kind) {
    // an interface instance: its variables become `inst.member` signals here
    ...
    let mut isc = Scope { prefix, ..Default::default() };
    if let Some(wp) = &d.interface_declaration_opt1 { self.params(&mut isc, &wp.with_parameter, &ov)?; }
    let items = crate::iface::items(d);
    for it in &items { self.pass1(&mut isc, it)?; }
    for it in &items { self.pass2(&mut isc, it, &cx)?; }
    for (n, id) in &isc.sigs { sc.sigs.insert(format!("{}.{}", iname, n), *id); }
    return Ok(());
}

// veryl-sim/src/iface.rs  modport()（節錄）
/// members of modport `mp`: (member, is output from the module's side)
pub fn modport(d: &InterfaceDeclaration, mp: &str) -> Result<Vec<(String, bool)>, String> {
    ...
    while i < body.len() {
        if body[i] == ".." {
            // ..input / ..output：其餘成員全部同方向
            // ..same(other) / ..converse(other)：沿用另一 modport 的方向（或反轉）
        }
        let (member, dir) = (body[i].clone(), ...);
        match dir {
            "input" => out.push((member, false)),
            "output" => out.push((member, true)),
            "import" => {} // a function import: nothing to connect
            o => return Err(...),
        }
        i += 3;
    }

// veryl-sim/src/elab.rs（節錄）
Direction::Modport(_) => {
    // `bus: modport Bus::master`: one port per member, named `bus.member`
    ...
    for (member, out) in crate::iface::modport(d, &mp)? {
        let ty = types.get(&member)...;
        let full = format!("{}.{}", name, member);
        let id = self.declare(&mut sc, &full, &ty);
        sc.ports.push((full, if out { Dir::Out } else { Dir::In }, id));
    }
    continue;
}

// veryl-sim/src/gen.rs（節錄）
pub fn for_indices(from: u128, to: u128, inclusive: bool, rev: bool, step: Option<(&str, u128)>) -> Result<Vec<u128>, String> {
    let end = if inclusive { to.checked_add(1)... } else { to };
    let mut v = vec![];
    let mut i = from;
    while i >= from && i < end {
        v.push(i);
        if v.len() > 1 << 20 { return Err("generate loop runs away".into()); }
        let next = match step {
            None | Some(("+=", _)) => i.checked_add(step.map(|s| s.1).unwrap_or(1)),
            Some(("-=", k)) => i.checked_sub(k),
            ... // *= <<= >>= 皆支援
        };
        match next { Some(n) if n != i => i = n, _ => break }
    }
    if rev { v.reverse(); }
    Ok(v)
}

// veryl-sim/src/elab.rs  gen_for()（節錄）
for i in idx {
    let mut inner = Scope { prefix: sc.prefix.clone(), sigs: sc.sigs.clone(),
                            params: sc.params.clone(), ports: vec![], imports: sc.imports.clone() };
    inner.params.insert(var.clone(), Val::new(32, i));   // ★ 迴圈變數 = 常數參數
    for it in &items { self.pass1(&mut inner, it)?; }
    for it in &items { self.pass2(&mut inner, it, cx)?; }
    // merge any newly declared signals back
    for (k, v) in &inner.sigs { sc.sigs.entry(k.clone()).or_insert(*v); }
}

// veryl-sim/src/elab.rs（節錄）
Statement::IfResetStatement(x) => {
    let (r, low) = cx.reset.ok_or("if_reset used without a reset signal")?;
    let active = Expr::Bin("==".into(), Box::new(Expr::Sig(r)), Box::new(Expr::Num(Val::new(1, if low { 0 } else { 1 }))));
    ...
}