2.7 閘級模擬#

// veryl-sim/src/gates.rs
/// Gives the gate netlist of a module for the given parameter overrides,
/// or None to simulate that module's RTL.
pub type GateFn<'a> = dyn Fn(&str, &HashMap<String, Val>) -> Result<Option<GateNetlist>, String> + 'a;

#[derive(Clone, Copy, PartialEq, Debug)]
pub enum Pin { C0, C1, W(u32) }       // 常數 0 / 常數 1 / 線網編號

#[derive(Clone, Debug)]
pub struct GCell {
    pub typ: String,                       // 單元型別，如 "SB_LUT4"
    pub conns: Vec<(String, Pin)>,         // (腳位名, 線網)
    pub params: Vec<(String, String)>,     // 參數（二進位字串）
}

#[derive(Clone, Debug)]
pub struct GateNetlist { pub ports: Vec<GPort>, pub cells: Vec<GCell> }

// veryl-sim/src/elab.rs  instantiate()（節錄）
let gate = match self.gates {
    Some(f) => {
        let mut ps: Vec<String> = ov.iter().map(|(n, v)| format!("{}={}", n, v.fmt_hex())).collect();
        ps.sort();
        let key = format!("{}#{}", kind, ps.join(","));
        if !self.gate_cache.contains_key(&key) { let g = f(&kind, &ov)?; self.gate_cache.insert(key.clone(), g); }
        self.gate_cache[&key].clone()
    }
    None => None,
};

// veryl-sim/src/gates.rs  elab_gates()（節錄）
pub fn elab_gates(&mut self, g: &GateNetlist, prefix: &str) -> R<Scope> {
    let mut sc = Scope { prefix: prefix.to_string(), ..Default::default() };
    let mut wires: HashMap<u32, usize> = HashMap::new();
    // ports: full-width signals, connected bit by bit to the wires
    for p in &g.ports {
        let full = if prefix.is_empty() { p.name.clone() } else { format!("{}.{}", prefix, p.name) };
        let id = self.new_sig(full, p.bits.len().max(1) as u32);
        ...
        for (i, b) in p.bits.iter().enumerate() {
            ...
            if p.output {
                let src = self.gw(&mut wires, prefix, *b);
                self.procs.push(Proc::Comb(vec![Stmt::Assign(..., src)]));   // 線網 → 埠
            } else if let Pin::W(_) = b {
                let w = self.gw(&mut wires, prefix, *b);
                self.procs.push(Proc::Comb(vec![Stmt::Assign(lv(sig_of(&w)), bit)]));  // 埠 → 線網
            }
        }
    }

// veryl-sim/src/gates.rs（節錄）
let comb: Option<(&str, Expr)> = match t {
    "$_NOT_" | "INV" => Some(("Y", not(i!(self, "A")))),
    "$_AND_" | "AND2" => Some(("Y", bin("&", i!(self, "A"), i!(self, "B")))),
    "$_XOR_" | "XOR2" => Some(("Y", bin("^", i!(self, "A"), i!(self, "B")))),
    "AOI21" => Some(("Y", not(bin("|", bin("&", i!(self, "A"), i!(self, "B")), i!(self, "C"))))),
    ...
    "$_MUX_" | "MUX2" => { ... Some(("Y", Expr::Tern(Box::new(s), Box::new(b), Box::new(a)))) }
    ...
};

// veryl-sim/src/gates.rs
// a mux tree over a truth table (not an indexed read): an x input
// then only matters where the table really depends on it, as in RTL
fn tree(init: u128, ins: &[Expr], k: usize, base: usize) -> Expr {
    if k == 0 { return Expr::Num(Val::new(1, (init >> base) & 1)); }
    let half = 1usize << (k - 1);
    let part = |b: usize| (init >> b) & ((1u128 << half) - 1);
    // input k-1 does not matter here: one subtree
    if part(base) == part(base + half) { return tree(init, ins, k - 1, base); }
    let (lo, hi) = (tree(init, ins, k - 1, base), tree(init, ins, k - 1, base + half));
    Expr::Tern(Box::new(ins[k - 1].clone()), Box::new(hi), Box::new(lo))
}

// veryl-sim/src/gates.rs（節錄）
"SB_CARRY" => {
    let (a, b, ci) = (i!(self, "I0"), i!(self, "I1"), i!(self, "CI"));
    Some(("CO", bin("|", bin("&", a.clone(), b.clone()), bin("&", bin("|", a, b), ci))))
}

// veryl-sim/src/gates.rs（節錄）
if t == "CCU2C" {
    // two carry-chain halves: S = LUT4 ^ CIN,
    // COUT = LUT4 ? CIN : LUT2 (INJECT1 = "YES" gates CIN and LUT2 off)
    let l4 = tree(init, &ins, 4, 0);
    let l2 = tree(init & 0xf, &ins[..2], 2, 0);
    let s = bin("^", l4.clone(), if inject { zero() } else { cin.clone() });
    let co = bin("|", bin("&", not(l4.clone()), if inject { zero() } else { l2 }), bin("&", l4, cin.clone()));
    ...
}

// veryl-sim/src/gates.rs（節錄）
let ff: Option<(&str, bool, Option<(&str, bool, bool, bool)>)> = if t == "TRELLIS_FF" {
    // ECP5: clock and LSR polarity muxes, REGSET value, SRMODE ASYNC or synchronous
    dpin = "DI";
    let r = c.conns.iter().any(|x| x.0 == "LSR").then(|| ("LSR", param("LSRMUX") != "INV", param("SRMODE") == "ASYNC", param("REGSET") == "SET"));
    Some(("CLK", param("CLKMUX") != "INV", r))
} else if let Some(k) = t.strip_prefix("SB_DFF") {
    let neg = k.starts_with('N');
    let k = k.trim_start_matches('N');
    let (sync, k) = if k.len() == 2 { (true, &k[1..]) } else { (false, k) };   // SB_DFFSR vs SB_DFFS
    let r = match k { "R" => Some(("R", true, !sync, false)), "S" => Some(("S", true, !sync, true)), _ => None };
    Some(("C", !neg, r))
} else if let Some(k) = t.starts_with("$_DFF_") ... // yosys 內部 $_DFF_PN0_ 等
...
if let Some((ck, rising, rst)) = ff {
    let (clk, d, q) = (sig_of(&i!(self, ck)), i!(self, dpin), sig_of(&i!(self, "Q")));
    let mut body = vec![Stmt::Assign(lv(q), d)];
    let mut rinfo = None;
    if let Some((rp, high, asynch, val)) = rst {
        let active = if high { r.clone() } else { not(r.clone()) };
        body = vec![Stmt::If(vec![(active, vec![Stmt::Assign(lv(q), Expr::Num(...))])], body)];
        rinfo = Some((sig_of(&r), !high, asynch));
        if asynch { self.watched.push(sig_of(&r)); }   // 非同步 reset 進敏感度
    }
    if clk == usize::MAX { continue; } // constant clock: never fires
    self.watched.push(clk);
    self.procs.push(Proc::Ff { clk, pos: rising, rst: rinfo.filter(|x| x.0 != usize::MAX), body });
}

// veryl-sim/src/gates.rs（節錄）
// the memory: `depth` element signals
let first = self.sim.sigs.len();
for k in 0..depth { self.sim.sigs.push(Signal { ..., val: Val::allx(width), ... }); }
self.sim.sigs[first].arr = Some(depth as u32);
...
// read register: one signal per data bit, then copied to the RDATA wires
let rreg = self.sim.sigs.len();
...
let read  = Stmt::If(vec![(re, vec![Stmt::Assign(lv(rreg), Expr::Elem(first, Box::new(raddr)))])], vec![]);
let write = Stmt::If(vec![(we, vec![Stmt::Assign(LValue { sig: first, sel: Sel::Elem(Box::new(waddr)) }, wdata)])], vec![]);
self.watched.push(clk);
self.procs.push(Proc::Ff { clk, pos: true, rst: None, body: vec![read, write] });