3.5 記憶體推斷：$mem 命名網協定與 SB_RAM40_4K#

/// How an array is used, recorded while it is elaborated as flip-flops: if
/// it is written only as whole elements from one always_ff (at most one
/// write per cycle) and read only as whole elements, it is a memory with one
/// write port and read ports.
#[derive(Default)]
struct MemInfo {
    bad: bool,
    /// (block, clock, rising edge, we, waddr, wdata)
    write: Option<(usize, Bit, bool, Bit, Vec<Bit>, Vec<Bit>)>,
    /// (address, data placeholder wires)
    reads: Vec<(Vec<Bit>, Vec<Bit>)>,
}

let ok = matches!(sel, Sel::Index(_)) && val.len() == ew as usize && self.ff.is_some()
    && env.get(&we).map(|v| v[0] == Bit::C0).unwrap_or(false) && !env.contains_key("$done");
if ok {
    env.insert(we, vec![Bit::C1]);
    env.insert(mem_key(name, "wa"), pad(&idx, wa));
    env.insert(mem_key(name, "wd"), val.to_vec());
} else {
    self.mems.entry(key).or_default().bad = true;
}

if let Some((_, r)) = self.mems.get(&key).and_then(|m| m.reads.iter().find(|(a, _)| *a == idx)) {
    return Ok(r.clone());
}
let r = self.b.wires(v.len() as u32);
for (p, d) in r.iter().zip(&v) { if let Bit::W(w) = p { self.alias.insert(*w, *d); } }
self.mems.entry(key).or_default().reads.push((idx, r.clone()));
return Ok(r);

for (q, m) in mems {
    let (_, ck, _, we, wa, wd) = m.write.as_ref().unwrap();
    mem_nets.push((format!("$mem:{}:clk", q), vec![*ck]));
    mem_nets.push((format!("$mem:{}:we",  q), vec![*we]));
    mem_nets.push((format!("$mem:{}:wa",  q), wa.clone()));
    mem_nets.push((format!("$mem:{}:wd",  q), wd.clone()));
    for (i, (ra, rd)) in m.reads.iter().enumerate() {
        mem_nets.push((format!("$mem:{}:ra{}", q, i), ra.clone()));
        mem_nets.push((format!("$mem:{}:rd{}", q, i), rd.clone()));
    }
}

let plain_ff = |i: usize| nl.cells[i].typ == "$_DFF_P_" && nl.cells[i].port("C") == Some(clk);
// the storage: rising-edge flip-flops on the write clock ...
for (k, b) in store.iter().enumerate() {
    match q_cell.get(b) { Some(&i) if plain_ff(i) => elems.push(i),
                          Some(_) => continue 'mem,       // 結構不符：放棄
                          None => missing[k % width] = true }
}

} else if p == "B" && c.typ == "$_MUX_" && !port_bits.contains(&c.out()) {
    // enable: D = en ? rd : Q
    let uu = users.get(&c.out())...;
    if uu.len() != 1 || uu[0].1 != "D" || !plain_ff(uu[0].0)
        || c.port("A") != Some(nl.cells[uu[0].0].out()) { continue 'mem; }
    gone.push(i);
    (uu[0].0, c.port("S").unwrap())
}

let mode = match m.depth { 0..=256 => 0, 257..=512 => 1, 513..=1024 => 2, _ => 3 };
let bw = 16 >> mode;               // 16/8/4/2 bits per word
let blocks = m.width.div_ceil(bw);
for r in &m.reads {
    for k in 0..blocks {
        let mut conns = vec![("RCLK", m.clk), ("RCLKE", r.en), ("RE", Bit::C1),
                             ("WCLK", m.clk), ("WCLKE", Bit::C1), ("WE", m.we)];
        for i in 0..11 { conns.push((RADDR[i], a(&r.addr, i))); conns.push((WADDR[i], a(&m.waddr, i))); }
        ...
        let mut params = vec![("READ_MODE", format!("{:032b}", mode)),
                              ("WRITE_MODE", format!("{:032b}", mode))];
        for name in INIT { params.push((name, "0".repeat(256))); }
        params.push((SLOT, format!("{}:{}", m.name, k)));
        rams.push(Cell { typ: "SB_RAM40_4K".into(), conns, params });
    }
}

pub const SLOT: &str = "MEM_SLOT";

/// Give memory `name` initial contents in a mapped iCE40 netlist
pub fn set_mem_init(nl: &mut Netlist, name: &str, words: &[u64]) -> usize {
    for c in nl.cells.iter_mut().filter(|c| c.typ == "SB_RAM40_4K") {
        let Some((m, k, mode)) = slot_of(c) else { continue };
        if m != name { continue; }
        let init = init_strings(mode, k, words);
        for (p, v) in c.params.iter_mut() {
            if let Some(i) = INIT.iter().position(|x| x == p) { *v = init[i].clone(); }
        }
    }
}

module TinyMem {
    input clk: clock;
    input we: logic<1>;
    input waddr: logic<6>;
    input wdata: logic<8>;
    input raddr: logic<6>;
    output rdata: logic<8>;
    var mem: logic<8>[64];
    always_ff {
        if we { mem[waddr] = wdata; }
    }
    always_ff {
        rdata = mem[raddr];        // 同步讀：rdata 是暫存器
    }
}