4.5 讀懂 chipdb：pnr/chipdb.rs#

.device 5k 38 38 43326 4417 4608  ...
.pins SG48
  A1  0 12 5 0 0
  ...
.net 17 12 3
  3 12  lutff_0/in_0
  4 12  sp4_h_r_0
  ...
.routing 3 12 4 1 1110 B0[0] B1[4]
.buffer  3 12 7 0 11 B1[3]
.logic_tile_bits 54 18
  LC_0  B0[21] B0[22] B0[23] B0[24] ...
.io_tile_bits 18 18
  IOB_0.PINTYPE_0  B0[2] B0[3] ...

// chipdb.rs:117-128
pub fn default_path() -> Option<String> {
    if let Ok(p) = std::env::var("VERYL_EDA_CHIPDB") { return Some(p); }
    let home = std::env::var("HOME").unwrap_or_default();
    let cands = [
        "/opt/homebrew/share/icebox/chipdb-5k.txt".to_string(),
        "/usr/local/share/icebox/chipdb-5k.txt".to_string(),
        "/usr/share/icebox/chipdb-5k.txt".to_string(),
        "/Users/Shared/ccc/oss-cad-suite/share/icebox/chipdb-5k.txt".to_string(),
        format!("{}/oss-cad-suite/share/icebox/chipdb-5k.txt", home),
    ];
    cands.into_iter().find(|p| std::path::Path::new(p).exists())
}

.ok_or("IceStorm chipdb-5k.txt not found (set VERYL_EDA_CHIPDB)")?;

if c.w == 0 { return Err(...); }                                  // 沒有 .device
if c.pins.is_empty() { return Err(...); }                         // 封裝名錯誤

// chipdb.rs:145
enum Sec {
    None,
    Pins(bool),          // bool = 這是目標封裝的腳位嗎
    Gbufin, Gbufpin, ExtraBits, Ieren, Colbuf,
    Bits(String),        // *_tile_bits 節（tile 型別名）
    Net(u32),            // .net <net-id>
    Mux(u8, u8, u32, u32), // (x, y, dst-net, group-id)
}

if p[0].starts_with('.') {
    sec = Sec::None;
    match p[0] {
        ".device" => {
            c.w = p[2].parse().unwrap_or(0);   // tile 寬
            c.h = p[3].parse().unwrap_or(0);   // tile 高
            let n: usize = p[4].parse().unwrap_or(0);  // net 總數
            // net 相關的平行陣列都按 n 配置
        }
        ".pins" => sec = Sec::Pins(p[1] == package),
        ".net"  => sec = Sec::Net(p[1].parse()?),
        ".buffer" | ".routing" => {
            // p: x y dst pattern bits...
            let bits: Vec<BitPos> = p[4..].iter().map(|b| bitpos(b)).collect()?;
            let n = c.groups.len() as u32;
            let g = *group_ix.entry((x, y, bits.clone())).or_insert(n);
            if g == n { c.groups.push(bits); }
            sec = Sec::Mux(x, y, dst, g);
        }
        t if t.ends_with("_tile_bits") => { /* 記 dims 與新的 tile_bits 表 */ }
        t if t.ends_with("_tile") => { /* 記 tile 位置與型別 */ }
        _ => {}
    }
    continue;
}

fn bitpos(s: &str) -> R<BitPos> {
    // "B12[34]"
    let s = s.strip_prefix('B').ok_or(...)?;
    let (r, c) = s.split_once('[').ok_or(...)?;
    ...
    Ok((r.parse()?, c.parse()?))
}

pub struct Chip {
    pub w: i32, pub h: i32,
    /// tile type ("logic", "io", "ramb", "ramt", "dsp0".., "ipcon") by position
    pub tile_type: HashMap<(i32, i32), String>,
    /// tile type -> (columns, rows)         // 該型別 tile 的位元矩陣尺寸
    pub dims: HashMap<String, (usize, usize)>,
    /// tile type -> function name -> bits   // "logic"/"LC_3" -> 20 個 BitPos
    pub tile_bits: HashMap<String, HashMap<String, Vec<BitPos>>>,
    /// (x, y, name) -> net                  // 導線名 -> 全域 net id
    pub by_name: HashMap<(i32, i32, String), u32>,
    /// per net: bounding box of the tiles it appears in
    pub net_box: Vec<(i16, i16, i16, i16)>,
    pub kind: Vec<Kind>,
    pub pips: Vec<Pip>,
    pub groups: Vec<Vec<BitPos>>,
    /// net -> pips leaving it               // 繞線搜尋的鄰接表
    pub fanout: Vec<Vec<u32>>,
    /// package pin -> (x, y, pio)
    pub pins: HashMap<String, (i32, i32, u8)>,
    pub gbufin: Vec<(i32, i32, u8)>,         // fabout -> glb_netwk_N 入口
    pub ieren: HashMap<(i32, i32, u8), (i32, i32, u8)>,
    pub colbuf_src: Vec<(i32, i32)>,
    pub extra_bits: HashMap<String, (usize, usize, usize)>,
}

pub struct Pip {
    pub x: u8, pub y: u8,
    pub src: u32, pub dst: u32,     // 驅動 net 與被驅動 net
    pub group: u32,                 // 這個 mux 輸入的配置位元組
    pub pat: u32,                   // 該組位元的值（bit i = group[i]）
}

// chipdb.rs:57-60
/// names the place and route looks up (`Chip::net`); other aliases are not kept
fn wanted(name: &str) -> bool {
    name.starts_with("lutff_") || name.starts_with("io_")
        || name.starts_with("glb_netwk_") || name == "fabout"
        || name.starts_with("carry_in") || name.starts_with("ram/")
}

// Sec::Net 的處理（chipdb.rs:215-222）
let b = &mut c.net_box[n];
*b = (b.0.min(x as i16), b.1.min(y as i16), b.2.max(x as i16), b.3.max(y as i16));
if c.net_label[n].2.is_empty() {
    c.net_label[n] = (x, y, p[2].to_string()); c.kind[n] = Kind::of(p[2]);
}
if wanted(p[2]) { c.by_name.insert((x, y, p[2].to_string()), n as u32); }

pub enum Kind {
    Other, Local, LutIn, LutOut, Ctrl,
    Glb, Glb2Local, Sp4H, Sp4V, Sp12H, Sp12V,
    Io, Carry, Fabout,
}

.routing 3 12 4 1 00 B0[3] B1[7]
.routing 3 12 4 5 10 B0[3] B1[7]
.routing 3 12 4 9 01 B0[3] B1[7]
.routing 3 12 4 13 11 B0[3] B1[7]

UP5K: 38×38 tiles ≈ 1444；logic/io tiles 各數百條 pip
整顆晶片 pips 總數約 30 萬級 —— Chip::parse 一次 parse 約百毫秒級

pub fn net(&self, x: i32, y: i32, name: &str) -> Option<u32>;   // by_name 查表
pub fn label(&self, n: u32) -> String;                          // 錯誤訊息用
pub fn bits(&self, ttype: &str, func: &str) -> R<&Vec<BitPos>>; // tile function bits