5.1 標準單元流程總覽#

// veryl-eda/src/asic/mod.rs（節錄）
fn physical(mapped: &Netlist, seed: u64, util: f64, extra_hold: f64) -> Result<...> {
    loop {
        placement = place::place(&mapped, seed, util, &Default::default(), None);
        // a short probe decides: a routable die needs few rounds
        let probe = route::route_with(&mapped, &placement, 8);
        if (probe.overflow > probe.iters[0] / 50 || probe.demand > 0.5) && util > 0.35 {
            util *= 0.8;   // 晶片面積太小，繞不動：換更大的 die
            continue;
        }
        routing = if probe.overflow == 0 { probe } else { route::route(&mapped, &placement) };
        break;
    }
    let mut timing = sta::analyze(&mapped, &placement, &routing, extra_hold);
    // timing-driven pass：以 criticality 加權線長再退火一次，取較快且可繞的結果
    let weights = timing_weights(&mapped, &timing.net_crit);
    ...
    let cts = cts::build(&mut mapped, &mut placement);   // 時鐘樹
    let mut routing = route::route(&mapped, &placement); // 含時鐘樹再繞
    // hold：在違規輸入前插延遲 BUF，最多三輪
    // PDN：taps、strap、filler，然後軌道級詳細繞線繞過它們
    let taps = pdn::insert_taps(&mapped, &mut placement);
    let pdn = pdn::build(&mapped, &placement, &taps);
    let detail = detail::route(&mapped, &placement, &routing, &pdn);
    ...
}

// veryl-eda/src/asic/mod.rs（節錄）
let lib_tech = !crate::pdk::tech().is_vlib();
let mut util = if lib_tech { 0.55 } else { 0.65 };
let (mapped, placement, ...) = loop {
    let r = physical(&mapped0, seed + attempt as u64, util, extra_hold)?;
    attempt += 1;
    if !lib_tech || (r.8.conflicts == 0 && r.8.opens == 0) || attempt >= 4 || r.9 < 0.2 { break ... }
    util = r.9 * 0.85;   // 詳細繞線失敗 → die 放大 15%
};

// veryl-eda/src/asic/lib.rs（節錄）
/// width in sites of a logical cell in the current technology
pub fn width(name: &str) -> u32 {
    crate::pdk::tech().binding(name).map(|b| b.width).unwrap_or_else(|| cell(name).width)
}
/// row height and site width (µm) of the current technology
pub fn row_h() -> f64 { crate::pdk::tech().row_h }
pub fn site_w() -> f64 { crate::pdk::tech().site_w }

let lib_rules = !tech.is_vlib();   // detail.rs：SKY130 專屬軌道規則
let vlib = tech.is_vlib();         // mod.rs def()：DEF 名稱與 pin 形狀

// veryl-eda/src/asic/mod.rs
pub struct Output {
    pub mapped: Netlist,          // 映射後網路
    pub placement: place::RowPlacement,
    pub routing: route::Routing,
    pub timing: sta::Timing,
    pub area: f64,                // 總 cell 面積 (µm²)
    pub counts: Vec<(String, usize)>,  // (單元型別, 數量)，多者在前
    pub fmax_wl: f64,             // 只看線長的佈局下的 Fmax（理想時鐘）
    pub fmax_ideal: f64,          // CTS 前的 Fmax
    pub cts: cts::Cts,
    pub hold_bufs: usize,         // 修 hold 插的 BUF 數
    pub detail: detail::Detail,
    pub pdn: pdn::Pdn,
    pub power: power::Power,
}

let dlen: HashMap<Bit, f64> = detail.nets.iter().map(|n| (n.bit, n.length)).collect();
for n in routing.nets.iter_mut() { if let Some(l) = dlen.get(&n.bit) { n.length = *l; } }
let timing = sta::analyze(&mapped, &placement, &routing, extra_hold);

area: 1234 cells, 8120 µm²   utilization 63%
cells: NAND2 ×412  DFF ×188  AOI21 ×97  ...
fmax (wirelength placement, ideal clock): 312 MHz
fmax (timing-driven,  ideal clock):       351 MHz   ← 時序驅動佈局的收益
fmax (after CTS, propagated clock):       338 MHz   ← 時鐘樹 skew 的代價
CTS: clk → 188 sinks, 23 CLKBUFs, 5 levels
hold buffers: 6
detail route: 0 conflicts, 0 opens