5.11 PDK 整合：Liberty、LEF、DEF#

// veryl-eda/src/pdk/liberty.rs
#[derive(Debug, Default, Clone)]
pub struct Group {
    pub kind: String,
    pub args: Vec<String>,
    /// simple (`name : value ;`) and complex (`name (v, ...) ;`) attributes, in order
    pub attrs: Vec<(String, Vec<String>)>,
    pub groups: Vec<Group>,
}

// veryl-eda/src/pdk/liberty.rs（節錄）
let s = String::from_utf8_lossy(&self.b[st..j.min(self.b.len())]).replace("\\\n", "").replace("\\\r\n", "");

// veryl-eda/src/pdk/liberty.rs（節錄）
impl Table {
    /// bilinear interpolation (extrapolating linearly past the ends)
    pub fn at(&self, x: f64, y: f64) -> f64 {
        let (x, y) = if self.transposed { (y, x) } else { (x, y) };
        let seg = |ix: &[f64], v: f64| -> (usize, f64) {
            if ix.len() < 2 { return (0, 0.0); }
            let mut k = 0;
            while k + 2 < ix.len() && v > ix[k + 1] { k += 1; }
            (k, (v - ix[k]) / (ix[k + 1] - ix[k]))
        };
        ...
        let r0 = g(i, j) + (g(i, j1) - g(i, j)) * fj;
        let r1 = g(i1, j) + (g(i1, j1) - g(i1, j)) * fj;
        r0 + (r1 - r0) * fi
    }
}

// veryl-eda/src/pdk/liberty.rs（節錄）
templates.insert(t.name().to_string(), (
    t.attr_list("index_1").map(...).unwrap_or_default(),
    t.attr_list("index_2").map(...).unwrap_or_default(),
    v1.contains("capacitance"),      // transposed
));

// veryl-eda/src/pdk/liberty.rs
/// truth table of `e` over `vars` (bit k of the index = vars[k])
pub fn truth(e: &Expr, vars: &[String]) -> u64 {
    let mut t = 0u64;
    for m in 0..(1u64 << vars.len()) {
        if e.eval(&|v: &str| vars.iter().position(|x| x == v).map(|k| m >> k & 1 == 1).unwrap_or(false)) { t |= 1 << m; }
    }
    t
}

// veryl-eda/src/pdk/lef.rs
pub struct Layer {
    pub name: String,
    pub kind: String,          // ROUTING, CUT, MASTERSLICE, ...
    pub horizontal: bool,
    pub pitch: (f64, f64),     // 繞線軌道間距
    pub offset: (f64, f64),    // 軌道 0 的位置 → Tech::track_x0/y0
    pub width: f64,
    pub spacing: f64,
    pub rpersq: f64,           // Ω/□ → STA 的線電阻
    pub cpersq: f64,           // pF/µm²
    pub edgecap: f64,          // pF/µm（邊緣）
}
pub struct Macro {
    pub name: String, pub class: String,
    pub w: f64, pub h: f64, pub site: String,
    pub pins: Vec<MacroPin>,   // 名稱/方向/USE/形狀矩形
    pub obs: Vec<Rect>,        // 障礙物
}

// veryl-eda/src/pdk/def.rs
pub struct Def {
    pub design: String,
    pub dbu: i64,
    pub die: (i64, i64, i64, i64),     // DIEAREA
    pub rows: Vec<Row>,                // ROW name site x y orient DO n BY 1 STEP sx sy
    pub comps: Vec<Component>,         // - name cell + PLACED ( x y ) orient
    pub pins: Vec<Pin>,
    pub nets: Vec<Net>,                // connections + ROUTED/VIA 記錄
    pub special: Vec<Net>,             // SPECIALNETS（電源）
}

// veryl-eda/src/pdk/def.rs（節錄）
if (c.x - r0.x) % sw != 0 || (c.y - r0.y) % sh != 0 { bad.push(format!("{} off the site grid ...")); }
...
let empty: usize = occ.iter().map(|r| r.iter().filter(|o| **o == 0).count()).sum();
if empty > 0 { bad.push(format!("{} sites without a cell or filler", empty)); }

// veryl-eda/src/pdk/mod.rs（節錄）
pub struct Tech {
    pub name: String,
    pub row_h: f64, pub site_w: f64, pub site: String,
    pub track_x0: f64, pub track_y0: f64,   // 繞線節點 (0,0) 的物理位置
    pub tracks: u32,
    pub layers: [String; 4], pub vias: [String; 3],   // 繞線層由下到上 + 層間 via
    pub pin_layer: String, pub pin_via: String,        // cell pin 層與它到 layers[0] 的 via
    pub sram: bool,                          // 記憶體是 SRAM 巨集（vlib）還是 flip-flop（SKY130）
    pub cells: HashMap<String, Binding>,
    pub fillers: Vec<(u32, String)>,
    pub tap: Option<(String, u32, f64)>,     // tap cell、寬、最大間距
    pub liberty: Option<liberty::Library>,
    pub lef: Option<lef::Lef>,
}

// veryl-eda/src/pdk/mod.rs
thread_local! {
    static CUR: RefCell<Option<Rc<Tech>>> = const { RefCell::new(None) };
    static VLIB: Rc<Tech> = Rc::new(vlib());
}
pub fn tech() -> Rc<Tech> { CUR.with(|c| c.borrow().clone()).unwrap_or_else(|| VLIB.with(|v| v.clone())) }
pub fn set_tech(t: Option<Rc<Tech>>) { CUR.with(|c| *c.borrow_mut() = t); }
pub fn with_tech<R>(t: Rc<Tech>, f: impl FnOnce() -> R) -> R {
    let old = CUR.with(|c| c.replace(Some(t)));
    struct Restore(Option<Rc<Tech>>);
    impl Drop for Restore { fn drop(&mut self) { let o = self.0.take(); CUR.with(|c| *c.borrow_mut() = o); } }
    let _r = Restore(old);
    f()
}

// veryl-eda/src/pdk/mod.rs（節錄）
/// logical cell -> (library cell, (logical pin, library pin), function over the logical pins)
pub const SKY130_HD: &[(&str, &str, &[(&str, &str)], Kind)] = &[
    ("INV", "inv_1", &[("A", "A"), ("Y", "Y")], Kind::Comb("!A")),
    ("AOI21", "a21oi_1", &[("A", "A1"), ("B", "A2"), ("C", "B1"), ("Y", "Y")], Kind::Comb("!((A&B)|C)")),
    ("MUX2", "mux2_1", &[("A", "A0"), ("B", "A1"), ("S", "S"), ("Y", "X")], Kind::Comb("(S&B)|(!S&A)")),
    ("DFFR", "dfrtp_1", &[("CK", "CLK"), ("D", "D"), ("RN", "RESET_B"), ("Q", "Q")],
        Kind::Ff { clk: "CK", clear: Some("!RN"), preset: None }),
    ...
];
pub const SKY130_PREFIX: &str = "sky130_fd_sc_hd__";

// veryl-eda/src/pdk/mod.rs（節錄）
for (logical, name, pins, kind) in SKY130_HD {
    let full = format!("{}{}", SKY130_PREFIX, name);
    let lc = lib.cell(&full).ok_or_else(|| format!("{} is not in the Liberty file", full))?;
    check_binding(lc, pins, kind)?;                      // 1. 邏輯函式等價
    let m = lef.macro_(&full).ok_or_else(...)?;          // 2. LEF 裡有這顆
    let access = access_points(m, &pins, "li1", ...)?;   // 3. pin 存取點找得到
    cells.insert(logical.to_string(), Binding { cell: full.clone(), pins, width: (m.w / site.w).round() as u32, access, area: lc.area });
}

// veryl-eda/src/pdk/mod.rs（節錄）
let same = |a: &liberty::Expr, b: &liberty::Expr| {
    let mut vars = vec![];
    a.vars(&mut vars);
    b.vars(&mut vars);
    liberty::truth(a, &vars) == liberty::truth(b, &vars)
};

// veryl-eda/src/pdk/mod.rs（節錄）
chk("clocked_on", &ff.clocked_on, clk)?;
chk("next_state", &ff.next_state, "D")?;
match (clear, &ff.clear) { (Some(w), Some(h)) => chk("clear", h, w)?, (None, None) => {}, _ => return Err(format!("{}: clear differs", lc.name)) }

// veryl-eda/src/pdk/mod.rs（節錄）
pub struct Binding {
    pub cell: String,                          // 庫名
    pub pins: Vec<(&'static str, String)>,     // (邏輯 pin, 庫 pin)
    pub width: u32,                            // 佔幾個 site
    pub access: Vec<(&'static str, u32, u32, f64)>,  // pin 存取點
    pub area: f64,
}

// veryl-eda/src/pdk/mod.rs（節錄）
pub fn to_library(nl: &crate::netlist::Netlist) -> crate::netlist::Netlist {
    let t = tech();
    let mut out = nl.clone();
    if t.is_vlib() { return out; }
    for c in out.cells.iter_mut() {
        let Some(b) = t.binding(&c.typ) else { continue };
        for (p, _) in c.conns.iter_mut() { *p = static_pin(b.lib_pin(p)); }
        c.typ = b.cell.clone();
    }
    out
}

// veryl-eda/src/pdk/mod.rs（節錄）
// 組合 cell：
for o in c.outputs() {
    if let Some(f) = o.function.as_deref().and_then(|f| liberty::function(f).ok()) {
        s += &format!("  assign {} = {};\n", o.name, f.verilog());
    }
}
// flip-flop：clocked_on 的運算式決定 posedge/negedge、clear/preset 決定 always 的條件鏈
s += &format!("  initial {} = 1'b0;\n  always @({}) {}{} <= {};\n", q, sens.join(" or "), body, q, d);

module sky130_fd_sc_hd__dfrtp_1 (input CLK, input D, input RESET_B, output reg Q);
  initial Q = 1'b0;
  always @(posedge CLK or negedge RESET_B) if (!RESET_B) Q <= 1'b0; else Q <= D;
endmodule