5.8 電源網路（PDN）#

// veryl-eda/src/asic/power.rs（模組註解節錄）
//! IR drop: each cell draws its average current from the VDD rail of its
//! row (and returns it on the VSS rail); a rail segment between two straps
//! is a resistive line fed at both ends (only one end before the first /
//! after the last strap), so a load I at distance x0 from one end of a
//! segment of length L drops the voltage at x by r·I·min(x,x0)·(L−max(x,x0))/L.

// veryl-eda/src/asic/pdn.rs
pub struct Pdn {
    /// row boundaries 0..=rows: VDD on odd ones, VSS on even ones
    pub rails: u32,
    /// straps: (first track x, VDD?)
    pub straps: Vec<(u32, bool)>,
    /// via stacks: (track x, track y, VDD?)
    pub vias: Vec<(u32, u32, bool)>,
    /// filler cells: (row, site, width in sites)
    pub fillers: Vec<(u32, u32, u32)>,
    /// well taps: (row, site)
    pub taps: Vec<(u32, u32)>,
    pub tap_viol: usize,
}

// veryl-eda/src/asic/pdn.rs（節錄，build）
for r in 0..=pl.rows {
    let vdd = r % 2 == 1;
    for &(x, sv) in &straps {
        if sv == vdd { ... vias.push((x + dx, r * TRACKS, vdd)); }
    }
}

// veryl-eda/src/asic/pdn.rs
/// strap pair pitch in tracks (40 µm)
pub const STRAP_PITCH: u32 = 80;
pub const STRAP_W: u32 = 2;

// veryl-eda/src/asic/pdn.rs（節錄）
let io_cols: Vec<u32> = pl.pins.iter().map(|p| (p.x / site_w()).round() as u32).collect();
let side = if crate::pdk::tech().is_vlib() { 0 } else { 3 };
let clear = |x: u32| (0..STRAP_W * 2 + 2 + 2 * side).all(|d| !io_cols.contains(&(x + d).wrapping_sub(side)));

// veryl-eda/src/asic/pdn.rs（節錄）
let mut vias = vec![];
for r in 0..=pl.rows {
    let vdd = r % 2 == 1;
    for &(x, sv) in &straps {
        if sv == vdd { for dx in 0..STRAP_W { if lib && (x + dx) % 2 == 1 { continue; } vias.push((x + dx, r * TRACKS, vdd)); } }
    }
}

// veryl-eda/src/asic/pdn.rs
pub fn blocked(&self, ny: u32) -> Vec<(usize, u32, u32)> {
    let lib = !crate::pdk::tech().is_vlib();
    let mut v = vec![];
    for &(x, _) in &self.straps {
        // a library's wide straps keep the neighbouring met4 tracks clear too
        let (a, b) = if lib { (x.saturating_sub(2), x + STRAP_W + 2) } else { (x, x + STRAP_W) };
        for xx in a..b { for y in 0..ny { v.push((LAYERS - 1, xx, y)); } }
    }
    for &(x, y, _) in &self.vias {
        for l in 0..LAYERS - 1 { v.push((l, x, y)); }
        if lib { /* via stack 的 met2/met3 pad 佔掉鄰近節點 */ ... }
    }
    v
}

// veryl-eda/src/asic/pdn.rs
pub const FILLERS: [u32; 4] = [8, 4, 2, 1];
...
let mut left = run;
let mut x = s;
while left > 0 {
    let w = *FILLERS.iter().find(|&&f| f <= left).unwrap();
    fillers.push((r, x, w));
    x += w;
    left -= w;
}

// veryl-eda/src/asic/pdn.rs
/// tap spacing (µm) and the largest allowed distance to one
pub const TAP_PITCH: f64 = 20.0;
pub const TAP_MAX: f64 = 14.0;

// veryl-eda/src/asic/pdn.rs（節錄）
if let Some(s) = (0..6).flat_map(|d| [x - d, x + d]).find(|&s| fits(s, &row, &tap_x)) { tap_x.push(s); continue; }
// open a gap: the cell edge nearest x, the nearest free run of tw sites to its right (or left), shift between
let free_right = (x..n - tw + 1).find(|&s| fits(s, &row, &tap_x));

// veryl-eda/src/asic/power.rs（節錄）
let rate = if clock.contains(b) { 2.0 } else { act.rate.get(b).copied().unwrap_or(0.0) };
let e = 0.5 * c * v2 * rate;
if clock.contains(b) { e_clock += e } else { e_nets += e }

if c.is_ff() { e += 3.0; } // clocking every cycle
if c.typ == "CLKBUF" { e += 0.4 * w * 2.0; } else {
    let rate = act.rate.get(&c.out()).copied().unwrap_or(0.0);
    e += 0.4 * w * rate;
}

let ea = 0.08 * width * depth.sqrt();
let es = (r + wr) * ea;

let leak_nw: Vec<f64> = nl.cells.iter().map(|c| if c.typ == "SRAM" {
    0.02 * (param(c, "DEPTH") * param(c, "WIDTH")) as f64
} else { 0.25 * dims(c).0 as f64 }).collect();

// veryl-eda/src/asic/power.rs（節錄）
drop += if a.is_infinite() { amp * RAIL_R * (b - x.max(x0)) }       // fed at b only
    else if b.is_infinite() { amp * RAIL_R * (x.min(x0) - a) }      // fed at a only
    else { let l = b - a; amp * RAIL_R * (x.min(x0) - a) * (b - x.max(x0)) / l };
...
ir[i] += drop * 1e3;   // mV

let rails: Vec<u32> = (r..=r + h).collect();
for k in &rails { rail_loads.entry(*k).or_default().push((i, amps / rails.len() as f64 * 2.0)); }