5.9 版圖建構與 DRC#

// veryl-eda/src/asic/layout.rs
/// a rectangle (nm) on a layer; net: index into `Layout::nets` (usize::MAX = none)
pub struct Shape { pub layer: u8, pub x0: i64, pub y0: i64, pub x1: i64, pub y1: i64, pub net: usize }

pub struct Layout {
    pub layers: Vec<String>,          // ["li1", "mcon", "met1", "via", "met2", ..., "met5"]
    pub shapes: Vec<Shape>,
    pub insts: Vec<Inst>,             // cell instances（DEF 的 components）
    pub nets: Vec<String>,            // 0 = VDD, 1 = VSS
    pub net_of: HashMap<Bit, usize>,
    pub labels: Vec<(u8, i64, i64, String)>,   // IO pin 標籤
    pub die: (i64, i64),
}

pub const LAYERS: [&str; 11] = ["li1", "mcon", "met1", "via", "met2", "via2", "met3", "via3", "met4", "via4", "met5"];

// veryl-eda/src/asic/layout.rs（節錄）
let rail_w = 480;                                  // nm，0.48 µm 寬的 M1 rail
let (rail, top) = (li(&tech.layers[0])?, li(&tech.layers[3])?);
for r in 0..o.pdn.rails {
    let net = if r % 2 == 1 { 0 } else { 1 };
    let y = nm(r as f64 * rh);
    shapes.push(Shape { layer: rail, x0: 0, y0: y - rail_w / 2, x1: nm(pl.w), y1: y + rail_w / 2, net });
}

// veryl-eda/src/asic/layout.rs（節錄）
let (ux, uy) = (|x: u32| nm(x as f64 * sw + tech.track_x0), |y: u32| nm(y as f64 * tk + tech.track_y0));
let width = |n: &str| lef.layer(n).map(|l| nm(l.width)).unwrap_or(140);
...
let wire = |shapes: &mut Vec<Shape>, l: u8, w: i64, x0, y0, x1, y1, net| {
    let h = w / 2;
    shapes.push(Shape { layer: l, x0: x0.min(x1) - h, y0: y0.min(y1) - h,
                        x1: x0.max(x1) + h, y1: y0.max(y1) + h, net });
};

// veryl-eda/src/asic/layout.rs（節錄）
let put_via = |shapes: &mut Vec<Shape>, name: &str, x: i64, y: i64, net: usize| -> Result<(), String> {
    let v = lef.via(name).ok_or_else(|| format!("via {} not in the LEF", name))?;
    for r in &v.rects {
        let l = li(&r.layer)?;
        shapes.push(Shape { layer: l, x0: x + nm(r.x0), y0: y + nm(r.y0), x1: x + nm(r.x1), y1: y + nm(r.y1), net });
    }
    Ok(())
};

// veryl-eda/src/asic/layout.rs（節錄）
if l == 255 {
    let off = stub.get(&(x, y)).copied().unwrap_or(0.0);
    let off = nm(off);
    if off != 0 { wire(&mut shapes, gl[0], gw[0], ux(x), uy(y), ux(x) + off, uy(y), ni); }
    put_via(&mut shapes, &tech.pin_via, ux(x) + off, uy(y), ni)?;
}

// veryl-eda/src/asic/layout.rs（節錄）
// fill: pieces of one net on a metal layer that face each other closer than its
// spacing (neighbouring via pads) get the gap between them filled ...
if gy < 0 && gx > 0 && gx < sp {
    fills.push(Shape { layer: li, x0: p.x1.min(q.x1), x1: p.x0.max(q.x0),
                       y0: p.y0.min(q.y0), y1: p.y1.max(q.y1), net: p.net });
}

// veryl-eda/src/asic/drc.rs（註解節錄）
//! Rules from the technology LEF:
//! - short: two nets' shapes overlap on a layer
//! - spacing: two nets' shapes on a routing layer closer than its SPACING
//!   (notches inside one net's merged metal: `tools/gds_check.py`, KLayout)
//!   (cut layers: any two different cuts closer than the cut spacing)
//! - area: a via landing pad on a routing layer that no wire of its net
//!   extends, smaller than the layer's minimum AREA
//! - open: a net whose shapes (with the cells' pins) are not one piece
//! Wide-metal spacing tables, end-of-line and antenna rules are not checked.

// veryl-eda/src/asic/drc.rs
fn gap(a: &Shape, b: &Shape) -> i64 {
    let dx = (b.x0 - a.x1).max(a.x0 - b.x1).max(0);
    let dy = (b.y0 - a.y1).max(a.y0 - b.y1).max(0);
    if dx > 0 && dy > 0 { ((dx * dx + dy * dy) as f64).sqrt() as i64 } else { dx.max(dy) }
}

// veryl-eda/src/asic/drc.rs（節錄）
let own = nets.len();
nets.push(format!("{}/obs", inst.name));       // OBS：每個 instance 一個專屬「net」
for r in &m.obs {
    let Some(li) = layer_index(&r.layer) else { continue };
    let (x0, y0, x1, y1) = place(r);
    out.push(Shape { layer: li, x0, y0, x1, y1, net: own });
}
for p in &m.pins {
    let net = match p.usage.as_str() {
        "POWER" => 0, "GROUND" => 1,
        _ => { /* 綁定表：library pin → 邏輯 pin → 訊號 net */ ... }
    };
    ...
}

// veryl-eda/src/asic/drc.rs（節錄）
const BIN: i64 = 2000;
for (i, s) in shapes.iter().enumerate() {
    for bx in s.x0.div_euclid(BIN)..=s.x1.div_euclid(BIN) {
        for by in s.y0.div_euclid(BIN)..=s.y1.div_euclid(BIN) { bins.entry((s.layer, bx, by)).or_default().push(i); }
    }
}

# tools/gds_check.py（節錄）
rules = {(67, 20): ("li1", 170, 170), (68, 20): ("met1", 140, 140), (69, 20): ("met2", 140, 140),
         (70, 20): ("met3", 300, 300), (71, 20): ("met4", 300, 300),
         (67, 44): ("mcon", 0, 190), (68, 44): ("via", 0, 170),
         (69, 44): ("via2", 0, 200), (70, 44): ("via3", 0, 200)}
for (ln, dt), (name, width, space) in rules.items():
    li = ly.find_layer(ln, dt)
    r = db.Region(top.begin_shapes_rec(li)).merged()   # ← 合併！
    n = r.space_check(space).count() if space else 0
    w = r.width_check(width).count() if width else 0